riscv/rocket-chip
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bootrom: Adding bootrom parameters (#857)

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BootROM parameters currently control the boot rom address, size, and the
hang which essentially sets the reset vector. This commit allows specifying
different parameter values as required.
This commit is contained in:
Shreesha Srinath 2017-07-13 13:40:02 -07:00 committed by Henry Cook
parent b7f1ba3428
commit f2533ce825
2 changed files with 11 additions and 4 deletions
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2
src/main/scala/chip/Configs.scala
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@ -34,6 +34,8 @@ class BasePlatformConfig extends Config((site, here, up) => {
case SOCBusConfig => site(L1toL2Config)
case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
case PeripheryBusArithmetic => true
// Default BootROMParams
case PeripheryBootROMKey => BootROMParams()
// Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false
case JtagDTMKey => new JtagDTMKeyDefault()

11
src/main/scala/chip/RISCVPlatform.scala
View File

@ -100,10 +100,15 @@ trait HasPeripheryRTCCounterModuleImp extends LazyMultiIOModuleImp {
}
/** Adds a boot ROM that contains the DTB describing the system's coreplex. */
case class BootROMParams(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040)
case object PeripheryBootROMKey extends Field[BootROMParams]
trait HasPeripheryBootROM extends HasSystemNetworks with HasCoreplexRISCVPlatform {
val bootrom_address = 0x10000
val bootrom_size = 0x10000
val bootrom_hang = 0x10040
val bootROMParams = p(PeripheryBootROMKey)
val bootrom_address = bootROMParams.address
val bootrom_size = bootROMParams.size
val bootrom_hang = bootROMParams.hang
private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))