From f2533ce825a877ed5259525f0fda84affb373b97 Mon Sep 17 00:00:00 2001 From: Shreesha Srinath Date: Thu, 13 Jul 2017 13:40:02 -0700 Subject: [PATCH] bootrom: Adding bootrom parameters (#857) BootROM parameters currently control the boot rom address, size, and the hang which essentially sets the reset vector. This commit allows specifying different parameter values as required. --- src/main/scala/chip/Configs.scala | 2 ++ src/main/scala/chip/RISCVPlatform.scala | 13 +++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/main/scala/chip/Configs.scala b/src/main/scala/chip/Configs.scala index ca24d164..315e9c65 100644 --- a/src/main/scala/chip/Configs.scala +++ b/src/main/scala/chip/Configs.scala @@ -34,6 +34,8 @@ class BasePlatformConfig extends Config((site, here, up) => { case SOCBusConfig => site(L1toL2Config) case PeripheryBusConfig => TLBusConfig(beatBytes = 4) case PeripheryBusArithmetic => true + // Default BootROMParams + case PeripheryBootROMKey => BootROMParams() // Note that PLIC asserts that this is > 0. case IncludeJtagDTM => false case JtagDTMKey => new JtagDTMKeyDefault() diff --git a/src/main/scala/chip/RISCVPlatform.scala b/src/main/scala/chip/RISCVPlatform.scala index 514f05cc..bef01db8 100644 --- a/src/main/scala/chip/RISCVPlatform.scala +++ b/src/main/scala/chip/RISCVPlatform.scala @@ -63,7 +63,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD debug.clockeddmi.foreach { dbg => outer.coreplex.module.io.debug <> dbg } - val dtm = debug.systemjtag.map { sj => + val dtm = debug.systemjtag.map { sj => val dtm = Module(new DebugTransportModuleJTAG(p(DMKey).nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag @@ -100,10 +100,15 @@ trait HasPeripheryRTCCounterModuleImp extends LazyMultiIOModuleImp { } /** Adds a boot ROM that contains the DTB describing the system's coreplex. */ +case class BootROMParams(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) + +case object PeripheryBootROMKey extends Field[BootROMParams] + trait HasPeripheryBootROM extends HasSystemNetworks with HasCoreplexRISCVPlatform { - val bootrom_address = 0x10000 - val bootrom_size = 0x10000 - val bootrom_hang = 0x10040 + val bootROMParams = p(PeripheryBootROMKey) + val bootrom_address = bootROMParams.address + val bootrom_size = bootROMParams.size + val bootrom_hang = bootROMParams.hang private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb) val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))