riscv/rocket-chip
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Move branch resolution to M stage

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This commit is contained in:
Andrew Waterman
2014-04-07 15:58:49 -07:00
parent db59fc65ab
commit f235fa0db6
6 changed files with 374 additions and 325 deletions
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139
rocket/src/main/scala/btb.scala
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@@ -5,11 +5,53 @@ import Util._
import Node._
import uncore.constants.AddressConstants._
case class BTBConfig(entries: Int, nras: Int = 0, inOrder: Boolean = true) {
case class BTBConfig(entries: Int, nras: Int = 0) {
val matchBits = PGIDX_BITS
val pages0 = 1 + log2Up(entries) // is this sensible? what about matchBits?
val pages0 = 1 max log2Up(entries) // is this sensible?
val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
val opaqueBits = log2Up(entries)
val nbht = 1 << log2Up(entries * 2)
}
class RAS(implicit conf: BTBConfig) {
def push(addr: UInt): Unit = {
when (count < conf.nras) { count := count + 1 }
val nextPos = Mux(Bool(isPow2(conf.nras)) || pos > 0, pos+1, UInt(0))
stack(nextPos) := addr
pos := nextPos
}
def peek: UInt = stack(pos)
def pop: Unit = when (!isEmpty) {
count := count - 1
pos := Mux(Bool(isPow2(conf.nras)) || pos > 0, pos-1, UInt(conf.nras-1))
}
def clear: Unit = count := UInt(0)
def isEmpty: Bool = count === UInt(0)
private val count = Reg(init=UInt(0,log2Up(conf.nras+1)))
private val pos = Reg(init=UInt(0,log2Up(conf.nras)))
private val stack = Vec.fill(conf.nras){Reg(UInt())}
}
class BHTResp(implicit conf: BTBConfig) extends Bundle {
val index = UInt(width = log2Up(conf.nbht).max(1))
val value = UInt(width = 2)
}
class BHT(implicit conf: BTBConfig) {
def get(addr: UInt): BHTResp = {
val res = new BHTResp
res.index := addr(log2Up(conf.nbht)+1,2) ^ history
res.value := table(res.index)
res
}
def update(d: BHTResp, taken: Bool): Unit = {
table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
history := Cat(taken, history(log2Up(conf.nbht)-1,1))
}
private val table = Mem(UInt(width = 2), conf.nbht)
val history = Reg(UInt(width = log2Up(conf.nbht)))
}
class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
@@ -18,6 +60,7 @@ class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
val target = UInt(width = VADDR_BITS)
val returnAddr = UInt(width = VADDR_BITS)
val taken = Bool()
val isJump = Bool()
val isCall = Bool()
val isReturn = Bool()
val incorrectTarget = Bool()
@@ -28,31 +71,12 @@ class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
class BTBResp(implicit conf: BTBConfig) extends Bundle {
val taken = Bool()
val target = UInt(width = VADDR_BITS)
val opaque = UInt(width = conf.opaqueBits)
val entry = UInt(width = conf.opaqueBits)
val bht = new BHTResp
override def clone = new BTBResp().asInstanceOf[this.type]
}
class RAS(implicit conf: BTBConfig) {
def push(addr: UInt): Unit = {
when (count < conf.nras-1) { count := count + 1 }
stack(pos+1) := addr
pos := pos+1
}
def pop: UInt = {
count := count - 1
pos := pos - 1
stack(pos)
}
def clear: Unit = count := UInt(0)
def isEmpty: Bool = count === UInt(0)
require(isPow2(conf.nras))
private val count = Reg(init=UInt(0,log2Up(conf.nras+1)))
private val pos = Reg(init=UInt(0,log2Up(conf.nras)))
private val stack = Vec.fill(conf.nras){Reg(UInt())}
}
// fully-associative branch target buffer
class BTB(implicit conf: BTBConfig) extends Module {
val io = new Bundle {
@@ -73,6 +97,7 @@ class BTB(implicit conf: BTBConfig) extends Module {
val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
val useRAS = Vec.fill(conf.entries){Reg(Bool())}
val isJump = Vec.fill(conf.entries){Reg(Bool())}
private def page(addr: UInt) = addr >> conf.matchBits
private def pageMatch(addr: UInt) = {
@@ -94,48 +119,48 @@ class BTB(implicit conf: BTBConfig) extends Module {
val updatePageHit = pageMatch(update.bits.pc)
val updateHits = tagMatch(update.bits.pc, updatePageHit)
val taken = update.bits.incorrectTarget || update.bits.taken
val predicted_taken = update.bits.prediction.valid && update.bits.prediction.bits.taken
val correction = update.bits.incorrectTarget || update.bits.taken != predicted_taken
private var lfsr = LFSR16(update.valid)
def rand(width: Int) = {
lfsr = lfsr(lfsr.getWidth-1,1)
Random.oneHot(width, lfsr)
}
def randOrInvalid(valid: UInt) =
Mux(!valid.andR, PriorityEncoderOH(~valid), rand(valid.getWidth))
val idxRepl = randOrInvalid(idxValid.toBits)
val idxWen =
if (conf.inOrder) Mux(update.bits.prediction.valid, UIntToOH(update.bits.prediction.bits.opaque), idxRepl)
else updateHits | Mux(updateHits.orR, UInt(0), idxRepl)
val updateHit = update.bits.prediction.valid
val updateValid = update.bits.incorrectTarget || updateHit && Bool(conf.nbht > 0)
val updateTarget = updateValid && update.bits.incorrectTarget
val useUpdatePageHit = updatePageHit.orR
val doIdxPageRepl = !useUpdatePageHit && update.valid
val idxPageRepl = rand(conf.pages)
val idxPageUpdate = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val doIdxPageRepl = updateTarget && !useUpdatePageHit
val idxPageRepl = UInt()
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val idxPageUpdate = OHToUInt(idxPageUpdateOH)
val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
val samePage = page(update.bits.pc) === page(update_target)
val usePageHit = (pageHit & ~idxPageReplEn).orR
val doTgtPageRepl = !usePageHit && !samePage && update.valid
val tgtPageRepl = Mux(samePage, idxPageUpdate, idxPageUpdate(conf.pages-2,0) << 1 | idxPageUpdate(conf.pages-1))
val tgtPageUpdate = Mux(usePageHit, pageHit, tgtPageRepl)
val doTgtPageRepl = updateTarget && !samePage && !usePageHit
val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(conf.pages-2,0) << 1 | idxPageUpdateOH(conf.pages-1))
val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
val pageReplEn = idxPageReplEn | tgtPageReplEn
idxPageRepl := UIntToOH(Counter(update.valid && (doIdxPageRepl || doTgtPageRepl), conf.pages)._1)
when (update.valid && !(updateValid && !updateTarget)) {
val nextRepl = Counter(!updateHit && updateValid, conf.entries)._1
val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
when (update.valid) {
for (i <- 0 until conf.entries) {
when (idxWen(i)) {
idxValid(i) := taken
when (correction) {
when (waddr === i) {
idxValid(i) := updateValid
when (updateTarget) {
if (i == 0) assert(io.req === update.bits.target, "BTB request != I$ target")
idxs(i) := update.bits.pc
idxPages(i) := OHToUInt(idxPageUpdate)
idxPages(i) := idxPageUpdate
tgts(i) := update_target
tgtPages(i) := OHToUInt(tgtPageUpdate)
useRAS(i) := update.bits.isReturn
tgtPages(i) := tgtPageUpdate
useRAS(i) := update.bits.isReturn
isJump(i) := update.bits.isJump
}
}.elsewhen ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) {
idxValid(i) := false
@@ -143,7 +168,7 @@ class BTB(implicit conf: BTBConfig) extends Module {
}
require(conf.pages % 2 == 0)
val idxWritesEven = (idxPageUpdate & Fill(conf.pages/2, UInt(1,2))).orR
val idxWritesEven = (idxPageUpdateOH & Fill(conf.pages/2, UInt(1,2))).orR
def writeBank(i: Int, mod: Int, en: Bool, data: UInt) = {
for (i <- i until conf.pages by mod) {
@@ -167,15 +192,27 @@ class BTB(implicit conf: BTBConfig) extends Module {
io.resp.valid := hits.toBits.orR
io.resp.bits.taken := io.resp.valid
io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
io.resp.bits.opaque := OHToUInt(hits)
io.resp.bits.entry := OHToUInt(hits)
if (conf.nbht > 0) {
val bht = new BHT
val res = bht.get(io.req)
when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) }
when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
io.resp.bits.bht := res
}
if (conf.nras > 0) {
val ras = new RAS
when (!ras.isEmpty && Mux1H(hits, useRAS)) {
io.resp.bits.target := ras.pop
io.resp.bits.target := ras.peek
}
when (io.update.valid && io.update.bits.isCall) {
ras.push(io.update.bits.returnAddr)
when (io.update.valid) {
when (io.update.bits.isCall) {
ras.push(io.update.bits.returnAddr)
}.elsewhen (io.update.bits.isReturn && io.update.bits.prediction.valid) {
ras.pop
}
}
when (io.invalidate) { ras.clear }
}