diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala index 9f1e04cd..d4beed04 100644 --- a/rocket/src/main/scala/btb.scala +++ b/rocket/src/main/scala/btb.scala @@ -5,11 +5,53 @@ import Util._ import Node._ import uncore.constants.AddressConstants._ -case class BTBConfig(entries: Int, nras: Int = 0, inOrder: Boolean = true) { +case class BTBConfig(entries: Int, nras: Int = 0) { val matchBits = PGIDX_BITS - val pages0 = 1 + log2Up(entries) // is this sensible? what about matchBits? + val pages0 = 1 max log2Up(entries) // is this sensible? val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages val opaqueBits = log2Up(entries) + val nbht = 1 << log2Up(entries * 2) +} + +class RAS(implicit conf: BTBConfig) { + def push(addr: UInt): Unit = { + when (count < conf.nras) { count := count + 1 } + val nextPos = Mux(Bool(isPow2(conf.nras)) || pos > 0, pos+1, UInt(0)) + stack(nextPos) := addr + pos := nextPos + } + def peek: UInt = stack(pos) + def pop: Unit = when (!isEmpty) { + count := count - 1 + pos := Mux(Bool(isPow2(conf.nras)) || pos > 0, pos-1, UInt(conf.nras-1)) + } + def clear: Unit = count := UInt(0) + def isEmpty: Bool = count === UInt(0) + + private val count = Reg(init=UInt(0,log2Up(conf.nras+1))) + private val pos = Reg(init=UInt(0,log2Up(conf.nras))) + private val stack = Vec.fill(conf.nras){Reg(UInt())} +} + +class BHTResp(implicit conf: BTBConfig) extends Bundle { + val index = UInt(width = log2Up(conf.nbht).max(1)) + val value = UInt(width = 2) +} + +class BHT(implicit conf: BTBConfig) { + def get(addr: UInt): BHTResp = { + val res = new BHTResp + res.index := addr(log2Up(conf.nbht)+1,2) ^ history + res.value := table(res.index) + res + } + def update(d: BHTResp, taken: Bool): Unit = { + table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken)) + history := Cat(taken, history(log2Up(conf.nbht)-1,1)) + } + + private val table = Mem(UInt(width = 2), conf.nbht) + val history = Reg(UInt(width = log2Up(conf.nbht))) } class BTBUpdate(implicit conf: BTBConfig) extends Bundle { @@ -18,6 +60,7 @@ class BTBUpdate(implicit conf: BTBConfig) extends Bundle { val target = UInt(width = VADDR_BITS) val returnAddr = UInt(width = VADDR_BITS) val taken = Bool() + val isJump = Bool() val isCall = Bool() val isReturn = Bool() val incorrectTarget = Bool() @@ -28,31 +71,12 @@ class BTBUpdate(implicit conf: BTBConfig) extends Bundle { class BTBResp(implicit conf: BTBConfig) extends Bundle { val taken = Bool() val target = UInt(width = VADDR_BITS) - val opaque = UInt(width = conf.opaqueBits) + val entry = UInt(width = conf.opaqueBits) + val bht = new BHTResp override def clone = new BTBResp().asInstanceOf[this.type] } -class RAS(implicit conf: BTBConfig) { - def push(addr: UInt): Unit = { - when (count < conf.nras-1) { count := count + 1 } - stack(pos+1) := addr - pos := pos+1 - } - def pop: UInt = { - count := count - 1 - pos := pos - 1 - stack(pos) - } - def clear: Unit = count := UInt(0) - def isEmpty: Bool = count === UInt(0) - - require(isPow2(conf.nras)) - private val count = Reg(init=UInt(0,log2Up(conf.nras+1))) - private val pos = Reg(init=UInt(0,log2Up(conf.nras))) - private val stack = Vec.fill(conf.nras){Reg(UInt())} -} - // fully-associative branch target buffer class BTB(implicit conf: BTBConfig) extends Module { val io = new Bundle { @@ -73,6 +97,7 @@ class BTB(implicit conf: BTBConfig) extends Module { val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0)) val useRAS = Vec.fill(conf.entries){Reg(Bool())} + val isJump = Vec.fill(conf.entries){Reg(Bool())} private def page(addr: UInt) = addr >> conf.matchBits private def pageMatch(addr: UInt) = { @@ -94,48 +119,48 @@ class BTB(implicit conf: BTBConfig) extends Module { val updatePageHit = pageMatch(update.bits.pc) val updateHits = tagMatch(update.bits.pc, updatePageHit) - val taken = update.bits.incorrectTarget || update.bits.taken - val predicted_taken = update.bits.prediction.valid && update.bits.prediction.bits.taken - val correction = update.bits.incorrectTarget || update.bits.taken != predicted_taken - private var lfsr = LFSR16(update.valid) def rand(width: Int) = { lfsr = lfsr(lfsr.getWidth-1,1) Random.oneHot(width, lfsr) } - def randOrInvalid(valid: UInt) = - Mux(!valid.andR, PriorityEncoderOH(~valid), rand(valid.getWidth)) - val idxRepl = randOrInvalid(idxValid.toBits) - val idxWen = - if (conf.inOrder) Mux(update.bits.prediction.valid, UIntToOH(update.bits.prediction.bits.opaque), idxRepl) - else updateHits | Mux(updateHits.orR, UInt(0), idxRepl) + val updateHit = update.bits.prediction.valid + val updateValid = update.bits.incorrectTarget || updateHit && Bool(conf.nbht > 0) + val updateTarget = updateValid && update.bits.incorrectTarget val useUpdatePageHit = updatePageHit.orR - val doIdxPageRepl = !useUpdatePageHit && update.valid - val idxPageRepl = rand(conf.pages) - val idxPageUpdate = Mux(useUpdatePageHit, updatePageHit, idxPageRepl) + val doIdxPageRepl = updateTarget && !useUpdatePageHit + val idxPageRepl = UInt() + val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl) + val idxPageUpdate = OHToUInt(idxPageUpdateOH) val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0)) val samePage = page(update.bits.pc) === page(update_target) val usePageHit = (pageHit & ~idxPageReplEn).orR - val doTgtPageRepl = !usePageHit && !samePage && update.valid - val tgtPageRepl = Mux(samePage, idxPageUpdate, idxPageUpdate(conf.pages-2,0) << 1 | idxPageUpdate(conf.pages-1)) - val tgtPageUpdate = Mux(usePageHit, pageHit, tgtPageRepl) + val doTgtPageRepl = updateTarget && !samePage && !usePageHit + val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(conf.pages-2,0) << 1 | idxPageUpdateOH(conf.pages-1)) + val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl)) val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0)) val pageReplEn = idxPageReplEn | tgtPageReplEn + idxPageRepl := UIntToOH(Counter(update.valid && (doIdxPageRepl || doTgtPageRepl), conf.pages)._1) + + when (update.valid && !(updateValid && !updateTarget)) { + val nextRepl = Counter(!updateHit && updateValid, conf.entries)._1 + val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl) - when (update.valid) { for (i <- 0 until conf.entries) { - when (idxWen(i)) { - idxValid(i) := taken - when (correction) { + when (waddr === i) { + idxValid(i) := updateValid + when (updateTarget) { + if (i == 0) assert(io.req === update.bits.target, "BTB request != I$ target") idxs(i) := update.bits.pc - idxPages(i) := OHToUInt(idxPageUpdate) + idxPages(i) := idxPageUpdate tgts(i) := update_target - tgtPages(i) := OHToUInt(tgtPageUpdate) - useRAS(i) := update.bits.isReturn + tgtPages(i) := tgtPageUpdate + useRAS(i) := update.bits.isReturn + isJump(i) := update.bits.isJump } }.elsewhen ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) { idxValid(i) := false @@ -143,7 +168,7 @@ class BTB(implicit conf: BTBConfig) extends Module { } require(conf.pages % 2 == 0) - val idxWritesEven = (idxPageUpdate & Fill(conf.pages/2, UInt(1,2))).orR + val idxWritesEven = (idxPageUpdateOH & Fill(conf.pages/2, UInt(1,2))).orR def writeBank(i: Int, mod: Int, en: Bool, data: UInt) = { for (i <- i until conf.pages by mod) { @@ -167,15 +192,27 @@ class BTB(implicit conf: BTBConfig) extends Module { io.resp.valid := hits.toBits.orR io.resp.bits.taken := io.resp.valid io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts)) - io.resp.bits.opaque := OHToUInt(hits) + io.resp.bits.entry := OHToUInt(hits) + + if (conf.nbht > 0) { + val bht = new BHT + val res = bht.get(io.req) + when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) } + when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false } + io.resp.bits.bht := res + } if (conf.nras > 0) { val ras = new RAS when (!ras.isEmpty && Mux1H(hits, useRAS)) { - io.resp.bits.target := ras.pop + io.resp.bits.target := ras.peek } - when (io.update.valid && io.update.bits.isCall) { - ras.push(io.update.bits.returnAddr) + when (io.update.valid) { + when (io.update.bits.isCall) { + ras.push(io.update.bits.returnAddr) + }.elsewhen (io.update.bits.isReturn && io.update.bits.prediction.valid) { + ras.pop + } } when (io.invalidate) { ras.clear } } diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 78eed730..2b59413c 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -17,6 +17,7 @@ trait ScalarOpConstants { val BR_GEU = Bits(7, 3) val PC_EX = UInt(0, 2) + val PC_MEM = UInt(1, 2) val PC_WB = UInt(2, 2) val PC_PCR = UInt(3, 2) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 2ada1dd7..4dabb716 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -27,9 +27,10 @@ class CtrlDpathIO(implicit conf: RocketConfiguration) extends Bundle val wb_load = Bool(OUTPUT) val ex_fp_val= Bool(OUTPUT) val mem_fp_val= Bool(OUTPUT) - val ex_wen = Bool(OUTPUT) - val ex_jalr = Bool(OUTPUT) - val ex_predicted_taken = Bool(OUTPUT) + val ex_wen = Bool(OUTPUT) + val ex_valid = Bool(OUTPUT) + val mem_jalr = Bool(OUTPUT) + val mem_branch = Bool(OUTPUT) val mem_wen = Bool(OUTPUT) val wb_wen = Bool(OUTPUT) val ex_mem_type = Bits(OUTPUT, 3) @@ -47,13 +48,13 @@ class CtrlDpathIO(implicit conf: RocketConfiguration) extends Bundle // inputs from datapath val inst = Bits(INPUT, 32) val jalr_eq = Bool(INPUT) - val ex_br_type = Bits(OUTPUT, SZ_BR) - val ex_br_taken = Bool(INPUT) + val mem_br_taken = Bool(INPUT) + val mem_misprediction = Bool(INPUT) val div_mul_rdy = Bool(INPUT) val ll_wen = Bool(INPUT) val ll_waddr = UInt(INPUT, 5) val ex_waddr = UInt(INPUT, 5) - val ex_rs = Vec.fill(2)(UInt(INPUT, 5)) + val mem_rs1_ra = Bool(INPUT) val mem_waddr = UInt(INPUT, 5) val wb_waddr = UInt(INPUT, 5) val status = new Status().asInput @@ -67,15 +68,15 @@ abstract trait DecodeConstants val xpr64 = Y val decode_default = - // fence.i - // jalr mul_val | sret - // fp_val | renx2 | div_val | | syscall - // | rocc_val | | renx1 s_alu1 mem_val | | wen | | | - // val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | brtype | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - List(N, X,X,X,BR_X, X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,CSR.X,N,X,X,X,X,X) + // jal fence.i + // | jalr mul_val | sret + // fp_val| | renx2 | div_val | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | wen | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next + // | | | | | | | | | | | | | | | | | | | | | | | | fence + // | | | | | | | | | | | | | | | | | | | | | | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | + List(N, X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,CSR.X,N,X,X,X,X,X) val table: Array[(UInt, List[UInt])] } @@ -83,225 +84,225 @@ abstract trait DecodeConstants object XDecode extends DecodeConstants { val table = Array( - // fence.i - // jalr mul_val | sret - // fp_val | renx2 | div_val | | syscall - // | rocc_val | | renx1 s_alu1 mem_val | | wen | | | - // val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | brtype | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - BNE-> List(Y, N,N,Y,BR_NE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BEQ-> List(Y, N,N,Y,BR_EQ, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BLT-> List(Y, N,N,Y,BR_LT, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BLTU-> List(Y, N,N,Y,BR_LTU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BGE-> List(Y, N,N,Y,BR_GE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BGEU-> List(Y, N,N,Y,BR_GEU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + // jal fence.i + // | jalr mul_val | sret + // fp_val| | renx2 | div_val | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | wen | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next + // | | | | | | | | | | | | | | | | | | | | | | | | fence + // | | | | | | | | | | | | | | | | | | | | | | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | + BNE-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SNE, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BEQ-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SEQ, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BLT-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLT, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BLTU-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLTU, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BGE-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGE, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BGEU-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGEU, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - JAL-> List(Y, N,N,Y,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - JALR-> List(Y, N,N,N,BR_X, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - AUIPC-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + JAL-> List(Y, N,N,N,Y,N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + JALR-> List(Y, N,N,N,N,Y,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + AUIPC-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - LB-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N), - LH-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N), - LW-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,N), - LD-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,N), - LBU-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,CSR.N,N,N,N,N,N,N), - LHU-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,CSR.N,N,N,N,N,N,N), - LWU-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,CSR.N,N,N,N,N,N,N), - SB-> List(Y, N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,CSR.N,N,N,N,N,N,N), - SH-> List(Y, N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,CSR.N,N,N,N,N,N,N), - SW-> List(Y, N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), - SD-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N), + LB-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N), + LH-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N), + LW-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,N), + LD-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,N), + LBU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,CSR.N,N,N,N,N,N,N), + LHU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,CSR.N,N,N,N,N,N,N), + LWU-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,CSR.N,N,N,N,N,N,N), + SB-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,CSR.N,N,N,N,N,N,N), + SH-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,CSR.N,N,N,N,N,N,N), + SW-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), + SD-> List(xpr64,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N), - AMOADD_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOXOR_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOSWAP_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOAND_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOOR_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMIN_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMINU_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAX_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAXU_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOADD_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOSWAP_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOXOR_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOAND_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOOR_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMIN_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMINU_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAX_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAXU_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOADD_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOXOR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOSWAP_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOAND_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOOR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMIN_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMINU_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMAX_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMAXU_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOADD_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOSWAP_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOXOR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOAND_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOOR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMIN_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMINU_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMAX_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOMAXU_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - LR_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - LR_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - SC_W-> List(Y, N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - SC_D-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + LR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + LR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + SC_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), + SC_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - LUI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ADDI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLTI -> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLTIU-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ANDI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ORI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - XORI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLLI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRLI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRAI-> List(Y, N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ADD-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SUB-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLT-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLTU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - AND-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - OR-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - XOR-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLL-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRL-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRA-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + LUI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + ADDI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLTI -> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLTIU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + ANDI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + ORI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + XORI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLLI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRLI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRAI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + ADD-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SUB-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLT-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLTU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + AND-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + OR-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + XOR-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRA-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ADDIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLLIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRLIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRAIW-> List(xpr64,N,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ADDW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SUBW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLLW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRLW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRAW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + ADDIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLLIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRLIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRAIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + ADDW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SUBW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SLLW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRLW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + SRAW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - MUL-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULH-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULHU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULHSU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), + MUL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), + MULH-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), + MULHU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), + MULHSU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), + MULW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - DIV-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - DIVU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REM-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REMU-> List(Y, N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - DIVW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - DIVUW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REMW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REMUW-> List(xpr64,N,N,N,BR_X, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + DIV-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + DIVU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + REM-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + REMU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + DIVW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + DIVUW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + REMW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + REMUW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - SCALL-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,Y,N,N,N), - SRET-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,Y,N,N,N,N), - FENCE-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,Y,N), - FENCE_I-> List(Y, N,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,Y,N,N,Y,N,N), - CSRRW-> List(Y, N,N,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N), - CSRRS-> List(Y, N,N,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N), - CSRRC-> List(Y, N,N,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N), - CSRRWI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N), - CSRRSI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N), - CSRRCI-> List(Y, N,N,N,BR_X, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N)) + SCALL-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,Y,N,N,N), + SRET-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,Y,N,N,N,N), + FENCE-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,Y,N), + FENCE_I-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,Y,N,N,Y,N,N), + CSRRW-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N), + CSRRS-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N), + CSRRC-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N), + CSRRWI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N), + CSRRSI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N), + CSRRCI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N)) } object FDecode extends DecodeConstants { val table = Array( - // fence.i - // jalr mul_val | sret - // fp_val | renx2 | div_val | | syscall - // | rocc_val | | renx1 s_alu1 mem_val | | wen | | | - // val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | brtype | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - FCVT_S_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJ_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJ_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJX_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJX_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJN_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJN_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMIN_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMIN_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMAX_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMAX_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FADD_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FADD_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSUB_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSUB_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMUL_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMUL_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMADD_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMADD_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMSUB_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMSUB_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMADD_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMADD_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMSUB_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMSUB_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCLASS_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCLASS_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FMV_X_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FMV_X_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_W_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_W_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_WU_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_WU_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_L_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_L_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_LU_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_LU_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FEQ_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FEQ_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLT_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLT_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLE_S-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLE_D-> List(Y, Y,N,N,BR_X, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FMV_S_X-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMV_D_X-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_W-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_W-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_WU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_WU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_L-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_L-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_LU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_LU-> List(Y, Y,N,N,BR_X, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FLW-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), - FLD-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,CSR.N,N,N,N,N,N,N), - FSW-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), - FSD-> List(Y, Y,N,N,BR_X, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N)) + // jal fence.i + // | jalr mul_val | sret + // fp_val| | renx2 | div_val | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | wen | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next + // | | | | | | | | | | | | | | | | | | | | | | | | fence + // | | | | | | | | | | | | | | | | | | | | | | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | + FCVT_S_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_D_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSGNJ_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSGNJ_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSGNJX_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSGNJX_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSGNJN_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSGNJN_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMIN_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMIN_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMAX_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMAX_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMUL_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMUL_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FNMADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FNMADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FNMSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FNMSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCLASS_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCLASS_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FMV_X_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FMV_X_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_W_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_W_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_WU_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_WU_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_L_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_L_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_LU_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FCVT_LU_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FEQ_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FEQ_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FLT_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FLT_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FLE_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FLE_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + FMV_S_X-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FMV_D_X-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_S_W-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_D_W-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_S_WU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_D_WU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_S_L-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_D_L-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_S_LU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FCVT_D_LU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + FLW-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), + FLD-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,CSR.N,N,N,N,N,N,N), + FSW-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), + FSD-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N)) } object RoCCDecode extends DecodeConstants { val table = Array( - // fence.i - // jalr mul_val | sret - // fp_val | renx2 | div_val | | syscall - // | rocc_val | | renx1 s_alu1 mem_val | | wen | | | - // val | | b | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | brtype | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - CUSTOM0-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM0_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM0_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM0_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM0_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM0_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM1-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM1_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM1_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM1_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM1_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM1_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM2-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM2_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM2_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM2_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM2_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM2_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM3-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM3_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM3_RS1_RS2-> List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM3_RD-> List(Y, N,Y,N,BR_X, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM3_RD_RS1-> List(Y, N,Y,N,BR_X, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM3_RD_RS1_RS2->List(Y, N,Y,N,BR_X, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N)) + // jal fence.i + // | jalr mul_val | sret + // fp_val| | renx2 | div_val | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | wen | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next + // | | | | | | | | | | | | | | | | | | | | | | | | fence + // | | | | | | | | | | | | | | | | | | | | | | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | + CUSTOM0-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM0_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM0_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM0_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM0_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM0_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM1-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM1_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM1_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM1_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM1_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM1_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM2-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM2_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM2_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM2_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM2_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM2_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM3-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM3_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM3_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + CUSTOM3_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM3_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + CUSTOM3_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N)) } class Control(implicit conf: RocketConfiguration) extends Module @@ -326,7 +327,7 @@ class Control(implicit conf: RocketConfiguration) extends Module val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table) - val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: (id_branch: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs + val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: (id_branch: Bool) :: (id_jal: Bool) :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0 val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: cs2 = cs1 val id_csr :: (id_fence_i: Bool) :: (id_sret: Bool) :: (id_syscall: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2 @@ -334,11 +335,10 @@ class Control(implicit conf: RocketConfiguration) extends Module val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_branch = Reg(Bool()) + val ex_reg_jal = Reg(Bool()) val ex_reg_jalr = Reg(Bool()) - val ex_reg_predicted_taken = Reg(Bool()) val ex_reg_btb_hit = Reg(Bool()) val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone) - val ex_reg_br_type = Reg(UInt()) val ex_reg_sret = Reg(Bool()) val ex_reg_wen = Reg(Bool()) val ex_reg_fp_wen = Reg(Bool()) @@ -357,6 +357,11 @@ class Control(implicit conf: RocketConfiguration) extends Module val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) + val mem_reg_branch = Reg(Bool()) + val mem_reg_jal = Reg(Bool()) + val mem_reg_jalr = Reg(Bool()) + val mem_reg_btb_hit = Reg(Bool()) + val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone) val mem_reg_sret = Reg(Bool()) val mem_reg_wen = Reg(Bool()) val mem_reg_fp_wen = Reg(Bool()) @@ -386,8 +391,10 @@ class Control(implicit conf: RocketConfiguration) extends Module val wb_reg_fp_val = Reg(Bool()) val wb_reg_div_mul_val = Reg(Bool()) - val take_pc = Bool() val take_pc_wb = Bool() + val take_pc_mem = io.dpath.mem_misprediction && (mem_reg_branch || mem_reg_jalr || mem_reg_jal) + val take_pc_mem_wb = take_pc_wb || take_pc_mem + val take_pc = take_pc_mem_wb val ctrl_killd = Bool() val ctrl_killx = Bool() val ctrl_killm = Bool() @@ -457,8 +464,8 @@ class Control(implicit conf: RocketConfiguration) extends Module when (ctrl_killd) { ex_reg_branch := false + ex_reg_jal := false ex_reg_jalr := false - ex_reg_predicted_taken := false ex_reg_btb_hit := false ex_reg_div_mul_val := Bool(false) ex_reg_mem_val := Bool(false) @@ -476,9 +483,8 @@ class Control(implicit conf: RocketConfiguration) extends Module } .otherwise { ex_reg_branch := id_branch + ex_reg_jal := id_jal ex_reg_jalr := id_jalr - ex_reg_predicted_taken := io.imem.btb_resp.valid && io.imem.btb_resp.bits.taken - when (id_branch) { ex_reg_br_type := id_br_type } ex_reg_btb_hit := io.imem.btb_resp.valid when (io.imem.btb_resp.valid) { ex_reg_btb_resp := io.imem.btb_resp.bits } ex_reg_div_mul_val := id_mul_val || id_div_val @@ -504,8 +510,7 @@ class Control(implicit conf: RocketConfiguration) extends Module ex_reg_div_mul_val && !io.dpath.div_mul_rdy val replay_ex_other = wb_dcache_miss && ex_reg_load_use || mem_reg_replay_next val replay_ex = replay_ex_structural || replay_ex_other - ctrl_killx := take_pc_wb || replay_ex - val take_pc_ex = ex_reg_jalr && !io.dpath.jalr_eq || io.dpath.ex_br_taken + ctrl_killx := take_pc_mem_wb || replay_ex // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type) @@ -513,13 +518,16 @@ class Control(implicit conf: RocketConfiguration) extends Module (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause), (ex_reg_fp_val && io.fpu.illegal_rm, UInt(Causes.illegal_instruction)))) - mem_reg_replay := replay_ex && !take_pc_wb - mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next + mem_reg_replay := !take_pc_mem_wb && replay_ex + mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt && !mem_reg_replay_next when (ex_xcpt) { mem_reg_cause := ex_cause } mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy when (ctrl_killx) { - mem_reg_valid := Bool(false) + mem_reg_valid := false + mem_reg_branch := false + mem_reg_jal := false + mem_reg_jalr := false mem_reg_csr := CSR.N mem_reg_wen := Bool(false) mem_reg_fp_wen := Bool(false) @@ -532,7 +540,12 @@ class Control(implicit conf: RocketConfiguration) extends Module mem_reg_xcpt := Bool(false) } .otherwise { - mem_reg_valid := ex_reg_valid + mem_reg_valid := ex_reg_valid + mem_reg_branch := ex_reg_branch + mem_reg_jal := ex_reg_jal + mem_reg_jalr := ex_reg_jalr + mem_reg_btb_hit := ex_reg_btb_hit + when (ex_reg_btb_hit) { mem_reg_btb_resp := ex_reg_btb_resp } mem_reg_csr := ex_reg_csr mem_reg_wen := ex_reg_wen mem_reg_fp_wen := ex_reg_fp_wen @@ -635,21 +648,21 @@ class Control(implicit conf: RocketConfiguration) extends Module // control transfer from ex/wb take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_sret - take_pc := take_pc_ex || take_pc_wb io.dpath.sel_pc := Mux(wb_reg_xcpt, PC_PCR, // exception Mux(wb_reg_sret, PC_PCR, // sret instruction Mux(replay_wb, PC_WB, // replay - PC_EX)))// branch/jal[r] + PC_MEM))) - io.imem.btb_update.valid := ex_reg_btb_hit || !take_pc_wb && (ex_reg_branch || ex_reg_jalr) && !ex_reg_xcpt - io.imem.btb_update.bits.prediction.valid := ex_reg_btb_hit - io.imem.btb_update.bits.prediction.bits := ex_reg_btb_resp - io.imem.btb_update.bits.taken := ex_reg_jalr || io.dpath.ex_br_taken ^ io.dpath.ex_predicted_taken - io.imem.btb_update.bits.incorrectTarget := ex_reg_jalr && !io.dpath.jalr_eq - io.imem.btb_update.bits.isCall := ex_reg_wen && io.dpath.ex_waddr(0) - io.imem.btb_update.bits.isReturn := ex_reg_jalr && io.dpath.ex_rs(0) === 1 + io.imem.btb_update.valid := (mem_reg_branch || mem_reg_jal || mem_reg_jalr) && !take_pc_wb && !mem_reg_xcpt + io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit + io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp + io.imem.btb_update.bits.taken := mem_reg_jal || mem_reg_branch && io.dpath.mem_br_taken + io.imem.btb_update.bits.incorrectTarget := take_pc_mem + io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr + io.imem.btb_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0) + io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra io.imem.req.valid := take_pc val bypassDst = Array(id_raddr1, id_raddr2) @@ -677,7 +690,7 @@ class Control(implicit conf: RocketConfiguration) extends Module io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr || io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr) - val id_ex_hazard = data_hazard_ex && (ex_reg_csr != CSR.N || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) || + val id_ex_hazard = data_hazard_ex && (ex_reg_csr != CSR.N || ex_reg_jalr || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) || fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val) // stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage. @@ -735,9 +748,10 @@ class Control(implicit conf: RocketConfiguration) extends Module io.dpath.div_mul_kill := mem_reg_div_mul_val && killm_common io.dpath.ex_fp_val:= ex_reg_fp_val io.dpath.mem_fp_val:= mem_reg_fp_val - io.dpath.ex_jalr := ex_reg_jalr - io.dpath.ex_predicted_taken := ex_reg_branch && ex_reg_btb_hit && ex_reg_btb_resp.taken + io.dpath.mem_jalr := mem_reg_jalr + io.dpath.mem_branch := mem_reg_branch io.dpath.ex_wen := ex_reg_wen + io.dpath.ex_valid := ex_reg_valid io.dpath.mem_wen := mem_reg_wen io.dpath.ll_ready := !wb_reg_wen io.dpath.wb_wen := wb_reg_wen && !replay_wb @@ -745,7 +759,6 @@ class Control(implicit conf: RocketConfiguration) extends Module io.dpath.csr := wb_reg_csr io.dpath.sret := wb_reg_sret io.dpath.ex_mem_type := ex_reg_mem_type - io.dpath.ex_br_type := Mux(ex_reg_branch, ex_reg_br_type, BR_N) ^ io.dpath.ex_predicted_taken io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val io.dpath.ex_rocc_val := ex_reg_rocc_val io.dpath.mem_rocc_val := mem_reg_rocc_val diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 0f446550..86c5d2fb 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -118,9 +118,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module } } - io.ctrl.ex_rs(0) := ex_reg_inst(19,15) - io.ctrl.ex_rs(1) := ex_reg_inst(24,20) - val bypass = Vec.fill(NBYP)(Bits()) bypass(BYP_0) := Bits(0) bypass(BYP_EX) := mem_reg_wdata @@ -169,11 +166,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1), e(0))) } - val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs(0), ex_reg_pc) - val ex_br_offset = Mux(io.ctrl.ex_predicted_taken, SInt(4), ex_imm(20,0).toSInt) - val ex_br64 = (ex_br_base + ex_br_offset) & SInt(-2) - val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs(0), ex_br64), vaSign(ex_reg_pc, ex_br64)) - val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0)) // D$ request interface (registered inside D$ module) // other signals (req_val, req_rdy) connect to control module @@ -196,17 +188,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module io.ptw.invalidate := pcr.io.fatc io.ptw.sret := io.ctrl.sret io.ptw.status := pcr.io.status - - // branch resolution logic - io.ctrl.jalr_eq := ex_rs(0) === id_pc.toSInt && ex_reg_inst(31,20) === UInt(0) - io.ctrl.ex_br_taken := - Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs(0) === ex_rs(1), - Mux(io.ctrl.ex_br_type === BR_NE, ex_rs(0) != ex_rs(1), - Mux(io.ctrl.ex_br_type === BR_LT, ex_rs(0).toSInt < ex_rs(1).toSInt, - Mux(io.ctrl.ex_br_type === BR_GE, ex_rs(0).toSInt >= ex_rs(1).toSInt, - Mux(io.ctrl.ex_br_type === BR_LTU, ex_rs(0) < ex_rs(1), - Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs(0) >= ex_rs(1), - io.ctrl.ex_br_type === BR_J)))))) // memory stage mem_reg_kill := ex_reg_kill @@ -255,11 +236,20 @@ class Datapath(implicit conf: RocketConfiguration) extends Module io.fpu.dmem_resp_type := io.dmem.resp.bits.typ io.fpu.dmem_resp_tag := dmem_resp_waddr + io.ctrl.mem_br_taken := mem_reg_wdata(0) + val mem_br_target = mem_reg_pc + + Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst), + Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4))) + val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(VADDR_BITS-1,0)), mem_br_target) + io.ctrl.mem_misprediction := mem_npc != Mux(io.ctrl.ex_valid, ex_reg_pc, id_pc) + io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1 + val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata) + // writeback stage when (!mem_reg_kill) { wb_reg_pc := mem_reg_pc wb_reg_inst := mem_reg_inst - wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata) + wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_int_wdata) } when (io.ctrl.mem_rocc_val) { wb_reg_rs2 := mem_reg_rs2 @@ -290,12 +280,12 @@ class Datapath(implicit conf: RocketConfiguration) extends Module // hook up I$ io.imem.req.bits.pc := - Mux(io.ctrl.sel_pc === PC_EX, ex_br_addr, + Mux(io.ctrl.sel_pc === PC_MEM, mem_npc, Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec, wb_reg_pc)).toUInt // PC_WB - io.imem.btb_update.bits.pc := ex_reg_pc + io.imem.btb_update.bits.pc := mem_reg_pc io.imem.btb_update.bits.target := io.imem.req.bits.pc - io.imem.btb_update.bits.returnAddr := io.dmem.req.bits.addr & SInt(-4) + io.imem.btb_update.bits.returnAddr := mem_int_wdata // for hazard/bypass opportunity detection io.ctrl.ex_waddr := ex_reg_inst(11,7) diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala index e4cbcd8c..4d9c54cb 100644 --- a/rocket/src/main/scala/dpath_alu.scala +++ b/rocket/src/main/scala/dpath_alu.scala @@ -14,10 +14,14 @@ object ALU val FN_OR = Bits(6) val FN_AND = Bits(7) val FN_SR = Bits(5) - val FN_SUB = Bits(8) - val FN_SLT = Bits(10) - val FN_SLTU = Bits(11) - val FN_SRA = Bits(13) + val FN_SEQ = Bits(8) + val FN_SNE = Bits(9) + val FN_SUB = Bits(10) + val FN_SRA = Bits(11) + val FN_SLT = Bits(12) + val FN_SGE = Bits(13) + val FN_SLTU = Bits(14) + val FN_SGEU = Bits(15) val FN_DIV = FN_XOR val FN_DIVU = FN_SR @@ -31,7 +35,9 @@ object ALU def isMulFN(fn: Bits, cmp: Bits) = fn(1,0) === cmp(1,0) def isSub(cmd: Bits) = cmd(3) - def isSLTU(cmd: Bits) = cmd(0) + def cmpUnsigned(cmd: Bits) = cmd(1) + def cmpInverted(cmd: Bits) = cmd(0) + def cmpEq(cmd: Bits) = !cmd(2) } import ALU._ @@ -52,8 +58,10 @@ class ALU(implicit conf: RocketConfiguration) extends Module val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2) // SLT, SLTU - val less = Mux(io.in1(63) === io.in2(63), sum(63), - Mux(isSLTU(io.fn), io.in2(63), io.in1(63))) + val cmp = cmpInverted(io.fn) ^ + Mux(cmpEq(io.fn), sum === UInt(0), + Mux(io.in1(63) === io.in2(63), sum(63), + Mux(cmpUnsigned(io.fn), io.in2(63), io.in1(63)))) // SLL, SRL, SRA val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUInt @@ -66,12 +74,12 @@ class ALU(implicit conf: RocketConfiguration) extends Module val out64 = Mux(io.fn === FN_ADD || io.fn === FN_SUB, sum, - Mux(io.fn === FN_SLT || io.fn === FN_SLTU, less, Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r, Mux(io.fn === FN_SL, shout_l, Mux(io.fn === FN_AND, io.in1 & io.in2, Mux(io.fn === FN_OR, io.in1 | io.in2, - /*FN_XOR*/ io.in1 ^ io.in2)))))) + Mux(io.fn === FN_XOR, io.in1 ^ io.in2, + /* all comparisons */ cmp)))))) val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31))) io.out := Cat(out_hi, out64(31,0)).toUInt diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index d9f49da8..5ea88247 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -70,7 +70,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu val pcp4_0 = s1_pc + UInt(c.ibytes) val pcp4 = Cat(s1_pc(VADDR_BITS-1) & pcp4_0(VADDR_BITS-1), pcp4_0(VADDR_BITS-1,0)) val icmiss = s2_valid && !icache.io.resp.valid - val predicted_npc = btbTarget /* zero if btb miss */ | Mux(btb.io.resp.bits.taken, UInt(0), pcp4) + val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4) val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & (c.databits/8)) === (s1_pc & (c.databits/8)))