tilelink2 RegisterRouterTest: work around firrtl warning
Using io.wready leads to verilog that reads from the output... Lint-[PCTIO-L] Ports coerced to inout /scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860 "io_wready" Port "io_wready" declared as output in module "RRTestCombinational_29" may need to be inout. Coercing to inout.
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@ -28,11 +28,13 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B
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val reg = Reg(UInt(width = bits))
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io.rvalid := rvalid(io.rready)
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io.wready := wready(io.wvalid)
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val rvalid_s = rvalid(io.rready)
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val wready_s = wready(io.wvalid)
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io.rvalid := rvalid_s
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io.wready := wready_s
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io.rdata := reg
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when (io.wvalid && io.wready) { reg := io.wdata }
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when (io.wvalid && wready_s) { reg := io.wdata }
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}
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object RRTestCombinational
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