From f0f553f2271f40d9260dcb7554380bce0537ea27 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 16 Sep 2016 14:49:43 -0700 Subject: [PATCH] tilelink2 RegisterRouterTest: work around firrtl warning Using io.wready leads to verilog that reads from the output... Lint-[PCTIO-L] Ports coerced to inout /scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860 "io_wready" Port "io_wready" declared as output in module "RRTestCombinational_29" may need to be inout. Coercing to inout. --- src/main/scala/uncore/tilelink2/RegisterRouterTest.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala index 04d73cf2..0c71428e 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala @@ -28,11 +28,13 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B val reg = Reg(UInt(width = bits)) - io.rvalid := rvalid(io.rready) - io.wready := wready(io.wvalid) + val rvalid_s = rvalid(io.rready) + val wready_s = wready(io.wvalid) + io.rvalid := rvalid_s + io.wready := wready_s io.rdata := reg - when (io.wvalid && io.wready) { reg := io.wdata } + when (io.wvalid && wready_s) { reg := io.wdata } } object RRTestCombinational