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tilelink2 RegisterRouterTest: work around firrtl warning

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Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
This commit is contained in:
Wesley W. Terpstra 2016-09-16 14:49:43 -07:00
parent 3fcc1a4460
commit f0f553f227
1 changed files with 5 additions and 3 deletions
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8
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
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@ -28,11 +28,13 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B
val reg = Reg(UInt(width = bits)) val reg = Reg(UInt(width = bits))
io.rvalid := rvalid(io.rready) val rvalid_s = rvalid(io.rready)
io.wready := wready(io.wvalid) val wready_s = wready(io.wvalid)
io.rvalid := rvalid_s
io.wready := wready_s
io.rdata := reg io.rdata := reg
when (io.wvalid && io.wready) { reg := io.wdata } when (io.wvalid && wready_s) { reg := io.wdata }
} }
object RRTestCombinational object RRTestCombinational