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add top that directly tests the TL -> AXI converters

This commit is contained in:
Howard Mao 2016-07-08 17:56:28 -07:00
parent b47f8fbc41
commit f03ffb32a0
2 changed files with 72 additions and 0 deletions

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@ -0,0 +1,52 @@
package rocketchip
import Chisel._
import cde.{Parameters, Field}
import groundtest._
import uncore.tilelink._
trait HasDirectMemtestParameters {
implicit val p: Parameters
lazy val tileSettings = p(GroundTestKey)(0)
lazy val nGens = tileSettings.uncached
}
class MemtestGenerators(implicit val p: Parameters) extends Module
with HasDirectMemtestParameters {
val io = new Bundle {
val mem = Vec(nGens, new ClientUncachedTileLinkIO)
val finished = Bool(OUTPUT)
}
val generators =
(0 until nGens).map(id => Module(new UncachedTileLinkGenerator(id)))
io.mem <> generators.map(_.io.mem)
io.finished := generators.map(_.io.finished).reduce(_ && _)
}
class DirectMemtestTop(topParams: Parameters) extends Module
with HasTopLevelParameters
with HasDirectMemtestParameters {
implicit val p = topParams
val io = new TopIO
// Not using the debug
io.debug.req.ready := Bool(false)
io.debug.resp.valid := Bool(false)
require(io.mmio_axi.isEmpty && io.mmio_ahb.isEmpty && io.mmio_tl.isEmpty)
require(io.mem_ahb.isEmpty && io.mem_tl.isEmpty)
require(nBanksPerMemChannel == nGens)
require(nMemChannels == 1)
require(nTiles == 1)
val memtest = Module(new MemtestGenerators()(outermostParams))
val mem_ic = Module(new TileLinkMemoryInterconnect(nGens, 1)(outermostParams))
mem_ic.io.in <> memtest.io.mem
io.mem_axi.zip(mem_ic.io.out).foreach { case (nasti, tl) =>
TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
}
when (memtest.io.finished) { stop() }
}

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@ -253,3 +253,23 @@ class WithPCIeMockupTest extends Config(
}) })
class PCIeMockupTestConfig extends Config( class PCIeMockupTestConfig extends Config(
new WithPCIeMockupTest ++ new GroundTestConfig) new WithPCIeMockupTest ++ new GroundTestConfig)
class WithDirectMemtest extends Config(
(pname, site, here) => {
val nGens = 8
pname match {
case GroundTestId => 0
case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens))
case GeneratorKey => GeneratorParameters(
maxRequests = 1024,
startAddress = 0)
// Kind of a Hack
case NAcquireTransactors => nGens - 2
case MIFTagBits => Dump("MIF_TAG_BITS", 2)
case NBanksPerMemoryChannel => nGens
case _ => throw new CDEMatchError
}
})
class DirectMemtestConfig extends Config(
new WithDirectMemtest ++ new GroundTestConfig)