From f03ffb32a01443c2c2a52a370fe02c5f916349e7 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Fri, 8 Jul 2016 17:56:28 -0700
Subject: [PATCH] add top that directly tests the TL -> AXI converters

---
 src/main/scala/DirectMemtest.scala | 52 ++++++++++++++++++++++++++++++
 src/main/scala/TestConfigs.scala   | 20 ++++++++++++
 2 files changed, 72 insertions(+)
 create mode 100644 src/main/scala/DirectMemtest.scala

diff --git a/src/main/scala/DirectMemtest.scala b/src/main/scala/DirectMemtest.scala
new file mode 100644
index 00000000..ee3a5ce5
--- /dev/null
+++ b/src/main/scala/DirectMemtest.scala
@@ -0,0 +1,52 @@
+package rocketchip
+
+import Chisel._
+import cde.{Parameters, Field}
+import groundtest._
+import uncore.tilelink._
+
+trait HasDirectMemtestParameters {
+  implicit val p: Parameters
+  lazy val tileSettings = p(GroundTestKey)(0)
+  lazy val nGens = tileSettings.uncached
+}
+
+class MemtestGenerators(implicit val p: Parameters) extends Module
+    with HasDirectMemtestParameters {
+  val io = new Bundle {
+    val mem = Vec(nGens, new ClientUncachedTileLinkIO)
+    val finished = Bool(OUTPUT)
+  }
+
+  val generators =
+    (0 until nGens).map(id => Module(new UncachedTileLinkGenerator(id)))
+
+  io.mem <> generators.map(_.io.mem)
+  io.finished := generators.map(_.io.finished).reduce(_ && _)
+}
+
+class DirectMemtestTop(topParams: Parameters) extends Module
+    with HasTopLevelParameters
+    with HasDirectMemtestParameters {
+  implicit val p = topParams
+  val io = new TopIO
+
+  // Not using the debug 
+  io.debug.req.ready := Bool(false)
+  io.debug.resp.valid := Bool(false)
+
+  require(io.mmio_axi.isEmpty && io.mmio_ahb.isEmpty && io.mmio_tl.isEmpty)
+  require(io.mem_ahb.isEmpty && io.mem_tl.isEmpty)
+  require(nBanksPerMemChannel == nGens)
+  require(nMemChannels == 1)
+  require(nTiles == 1)
+
+  val memtest = Module(new MemtestGenerators()(outermostParams))
+  val mem_ic = Module(new TileLinkMemoryInterconnect(nGens, 1)(outermostParams))
+
+  mem_ic.io.in <> memtest.io.mem
+  io.mem_axi.zip(mem_ic.io.out).foreach { case (nasti, tl) =>
+    TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
+  }
+  when (memtest.io.finished) { stop() }
+}
diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala
index f314b3ca..ad685acf 100644
--- a/src/main/scala/TestConfigs.scala
+++ b/src/main/scala/TestConfigs.scala
@@ -253,3 +253,23 @@ class WithPCIeMockupTest extends Config(
   })
 class PCIeMockupTestConfig extends Config(
   new WithPCIeMockupTest ++ new GroundTestConfig)
+
+class WithDirectMemtest extends Config(
+  (pname, site, here) => {
+    val nGens = 8
+    pname match {
+      case GroundTestId => 0
+      case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens))
+      case GeneratorKey => GeneratorParameters(
+        maxRequests = 1024,
+        startAddress = 0)
+      // Kind of a Hack
+      case NAcquireTransactors => nGens - 2
+      case MIFTagBits => Dump("MIF_TAG_BITS", 2)
+      case NBanksPerMemoryChannel => nGens
+      case _ => throw new CDEMatchError
+    }
+  })
+
+class DirectMemtestConfig extends Config(
+  new WithDirectMemtest ++ new GroundTestConfig)