riscv/rocket-chip
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fix coherence bug

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popping wrong store dependence queue
This commit is contained in:
Andrew Waterman 2012-03-16 01:24:07 -07:00
parent cfca2d1411
commit f0157b9e2a
1 changed files with 8 additions and 7 deletions
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5
rocket/src/main/scala/coherence.scala
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@ -295,8 +295,9 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
when(req_cmd.ready && req_cmd.valid) {
cmd_sent := Bool(true)
}
when(req_data.ready && req_data.valid) {
when(req_data.ready && at_front_of_dep_queue) {
pop_data := UFix(1) << tile_id
when (data.valid) {
mem_cnt := mem_cnt_next
when(mem_cnt_next === UFix(0)) {
pop_dep := UFix(1) << tile_id
@ -304,6 +305,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
}
}
}
}
def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
req_cmd.valid := Bool(true)
@ -391,7 +393,6 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
io.pop_p_rep := io.p_rep_cnt_dec
if(ntiles > 1) p_rep_count := p_rep_count - dec
when(p_rep_count === dec) {
io.pop_p_rep := Bool(true)
state := s_mem
}
}