riscv/rocket-chip
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Let user of CSRFile decide when to set tval

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I also renamed badaddr to tval (the correct name).
This commit is contained in:
Andrew Waterman 2018-02-06 14:05:03 -08:00
parent a59fc3bdaa
commit efc6c9cbd3
2 changed files with 9 additions and 11 deletions
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14
src/main/scala/rocket/CSR.scala
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@ -196,7 +196,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
val retire = UInt(INPUT, log2Up(1+retireWidth))
val cause = UInt(INPUT, xLen)
val pc = UInt(INPUT, vaddrBitsExtended)
val badaddr = UInt(INPUT, vaddrBitsExtended)
val tval = UInt(INPUT, vaddrBitsExtended)
val time = UInt(OUTPUT, xLen)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
@ -527,12 +527,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
assert(!reg_singleStepped || io.retire === UInt(0))
val epc = formEPC(io.pc)
val write_badaddr = exception && cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store,
Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)
val noCause :: mCause :: hCause :: sCause :: uCause :: Nil = Enum(5)
val xcause_dest = Wire(init = noCause)
@ -549,7 +543,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
reg_sepc := epc
reg_scause := cause
xcause_dest := sCause
reg_sbadaddr := badaddr_value
reg_sbadaddr := io.tval
reg_mstatus.spie := reg_mstatus.sie
reg_mstatus.spp := reg_mstatus.prv
reg_mstatus.sie := false
@ -558,7 +552,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
reg_mepc := epc
reg_mcause := cause
xcause_dest := mCause
reg_mbadaddr := badaddr_value
reg_mbadaddr := io.tval
reg_mstatus.mpie := reg_mstatus.mie
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
reg_mstatus.mie := false
@ -808,7 +802,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := cause
t.interrupt := cause(xLen-1)
t.tval := badaddr_value
t.tval := io.tval
}
def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = {

6
src/main/scala/rocket/RocketCore.scala
View File

@ -545,7 +545,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
csr.io.fcsr_flags := io.fpu.fcsr_flags
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.pc := wb_reg_pc
csr.io.badaddr := encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata)
val tval_valid = wb_xcpt && wb_cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store,
Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
io.ptw.ptbr := csr.io.ptbr
io.ptw.status := csr.io.status
io.ptw.pmp := csr.io.pmp