validate BTB address and use BTB for J/JAL/JR/JALR
even if we weren't using the BTB for JR/JALR, we'd need to flush the BTB on FENCE.I and on context switches, but validating its result suffices instead.
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2f8fcebea0
commit
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@ -39,6 +39,7 @@ class ioCtrlDpath extends Bundle()
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val wen = Bool('output);
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val wen = Bool('output);
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// instruction in execute is an unconditional jump
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// instruction in execute is an unconditional jump
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val ex_jmp = Bool('output);
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val ex_jmp = Bool('output);
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val ex_jr = Bool('output);
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// enable/disable interrupts
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// enable/disable interrupts
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val irq_enable = Bool('output);
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val irq_enable = Bool('output);
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val irq_disable = Bool('output);
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val irq_disable = Bool('output);
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@ -49,6 +50,7 @@ class ioCtrlDpath extends Bundle()
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// inputs from datapath
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// inputs from datapath
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val xcpt_ma_inst = Bool('input); // high on a misaligned/illegal virtual PC
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val xcpt_ma_inst = Bool('input); // high on a misaligned/illegal virtual PC
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val btb_hit = Bool('input);
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val btb_hit = Bool('input);
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val btb_match = Bool('input);
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val inst = Bits(32, 'input);
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val inst = Bits(32, 'input);
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val br_eq = Bool('input);
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val br_eq = Bool('input);
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val br_lt = Bool('input);
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val br_lt = Bool('input);
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@ -418,6 +420,11 @@ class rocketCtrl extends Component
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}
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}
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val jr_taken = (ex_reg_br_type === BR_JR);
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val j_taken = (ex_reg_br_type === BR_J);
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io.dpath.ex_jmp := j_taken;
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io.dpath.ex_jr := jr_taken;
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val beq = io.dpath.br_eq;
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val beq = io.dpath.br_eq;
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val bne = ~io.dpath.br_eq;
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val bne = ~io.dpath.br_eq;
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val blt = io.dpath.br_lt;
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val blt = io.dpath.br_lt;
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@ -431,11 +438,8 @@ class rocketCtrl extends Component
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(ex_reg_br_type === BR_LT) & blt |
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(ex_reg_br_type === BR_LT) & blt |
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(ex_reg_br_type === BR_LTU) & bltu |
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(ex_reg_br_type === BR_LTU) & bltu |
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(ex_reg_br_type === BR_GE) & bge |
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(ex_reg_br_type === BR_GE) & bge |
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(ex_reg_br_type === BR_GEU) & bgeu;
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(ex_reg_br_type === BR_GEU) & bgeu |
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j_taken; // treat J/JAL like a taken branch
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val jr_taken = (ex_reg_br_type === BR_JR);
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val j_taken = (ex_reg_br_type === BR_J);
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io.dpath.ex_jmp := j_taken;
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val mem_reg_div_mul_val = Reg(){Bool()};
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val mem_reg_div_mul_val = Reg(){Bool()};
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val mem_reg_eret = Reg(){Bool()};
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val mem_reg_eret = Reg(){Bool()};
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@ -537,7 +541,9 @@ class rocketCtrl extends Component
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val kill_mem = mem_hazard || mem_exception;
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val kill_mem = mem_hazard || mem_exception;
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// control transfer from ex/mem
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// control transfer from ex/mem
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val take_pc_ex = (ex_reg_btb_hit != br_taken) || jr_taken || j_taken
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val ex_btb_match = ex_reg_btb_hit && io.dpath.btb_match
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val br_jr_taken = br_taken || jr_taken
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val take_pc_ex = !ex_btb_match && br_jr_taken || ex_reg_btb_hit && !br_jr_taken
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val take_pc_mem = mem_exception || mem_reg_eret || replay_mem
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val take_pc_mem = mem_exception || mem_reg_eret || replay_mem
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val take_pc = take_pc_ex || take_pc_mem
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val take_pc = take_pc_ex || take_pc_mem
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@ -556,14 +562,13 @@ class rocketCtrl extends Component
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Mux(replay_mem, PC_MEM, // dtlb miss
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Mux(replay_mem, PC_MEM, // dtlb miss
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Mux(mem_exception, PC_EVEC, // exception
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Mux(mem_exception, PC_EVEC, // exception
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Mux(mem_reg_eret, PC_PCR, // eret instruction
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Mux(mem_reg_eret, PC_PCR, // eret instruction
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Mux(!ex_reg_btb_hit && br_taken, PC_BR, // mispredicted taken branch
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Mux(ex_reg_btb_hit && !br_jr_taken, PC_EX4, // mispredicted not taken branch
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Mux(j_taken, PC_BR, // jump
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Mux(!ex_btb_match && br_taken, PC_BR, // mispredicted taken branch
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Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch
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Mux(!ex_btb_match && jr_taken, PC_JR, // mispredicted jump register
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Mux(jr_taken, PC_JR, // jump register
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Mux(io.dpath.btb_hit, PC_BTB, // predicted PC from BTB
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Mux(io.dpath.btb_hit, PC_BTB, // predicted PC from BTB
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PC_4)))))))); // PC+4
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PC_4))))))); // PC+4
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io.dpath.wen_btb := ~ex_reg_btb_hit & br_taken & ~kill_ex & ~kill_mem;
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io.dpath.wen_btb := !ex_btb_match && br_jr_taken && !kill_ex;
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io.dpath.stallf :=
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io.dpath.stallf :=
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~take_pc &
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~take_pc &
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@ -47,7 +47,8 @@ class rocketDpath extends Component
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val alu = new rocketDpathALU();
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val alu = new rocketDpathALU();
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val ex_alu_out = alu.io.out;
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val ex_alu_out = alu.io.out;
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val ex_jr_target = ex_alu_out(VADDR_BITS-1,0);
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val ex_alu_adder_out = alu.io.adder_out;
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val ex_jr_target = ex_alu_adder_out(VADDR_BITS-1,0);
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val div = new rocketDivider(64);
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val div = new rocketDivider(64);
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val div_result = div.io.div_result_bits;
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val div_result = div.io.div_result_bits;
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@ -129,7 +130,7 @@ class rocketDpath extends Component
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val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
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val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
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btb.io.correct_target := ex_branch_target;
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btb.io.correct_target := Mux(io.ctrl.ex_jr, ex_jr_target, ex_branch_target);
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val if_next_pc =
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val if_next_pc =
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Mux(io.ctrl.sel_pc === PC_BTB, if_btb_target,
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Mux(io.ctrl.sel_pc === PC_BTB, if_btb_target,
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@ -156,6 +157,7 @@ class rocketDpath extends Component
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btb.io.hit ^^ io.ctrl.btb_hit;
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btb.io.hit ^^ io.ctrl.btb_hit;
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btb.io.wen ^^ io.ctrl.wen_btb;
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btb.io.wen ^^ io.ctrl.wen_btb;
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btb.io.correct_pc4 := ex_reg_pc_plus4;
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btb.io.correct_pc4 := ex_reg_pc_plus4;
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io.ctrl.btb_match := id_reg_pc === btb.io.correct_target;
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// instruction decode stage
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// instruction decode stage
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when (!io.ctrl.stalld) {
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when (!io.ctrl.stalld) {
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@ -297,7 +299,7 @@ class rocketDpath extends Component
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// D$ request interface (registered inside D$ module)
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req_addr := ex_alu_out(VADDR_BITS-1,0);
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io.dmem.req_addr := ex_alu_adder_out(VADDR_BITS-1,0);
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io.dmem.req_data := ex_reg_rs2;
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io.dmem.req_data := ex_reg_rs2;
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io.dmem.req_tag := ex_reg_waddr;
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io.dmem.req_tag := ex_reg_waddr;
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@ -14,6 +14,7 @@ class ioALU extends Bundle(){
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val in2 = UFix(64, 'input);
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val in2 = UFix(64, 'input);
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val in1 = UFix(64, 'input);
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val in1 = UFix(64, 'input);
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val out = UFix(64, 'output);
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val out = UFix(64, 'output);
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val adder_out = UFix(64, 'output);
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}
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}
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class rocketDpathALU extends Component
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class rocketDpathALU extends Component
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@ -54,6 +55,7 @@ class rocketDpathALU extends Component
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val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
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val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
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io.out := Cat(out_hi, out64(31,0)).toUFix
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io.out := Cat(out_hi, out64(31,0)).toUFix
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io.adder_out := adder_out
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}
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}
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}
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}
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