riscv/rocket-chip
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integrate updated rocket/uncore

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This commit is contained in:
Andrew Waterman 2012-10-18 17:51:41 -07:00
parent 6d49dc51a0
commit edf0eeed01
9 changed files with 56 additions and 46 deletions
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2
Makefrag
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@ -1,6 +1,6 @@
# Makefile snippet used by emulator/vlsi/fpga backends # Makefile snippet used by emulator/vlsi/fpga backends
MODEL := ReferenceChipTop MODEL := Top
CXX := g++ CXX := g++
CXXFLAGS := -O2 CXXFLAGS := -O2

2
chisel

@ -1 +1 @@
Subproject commit f07a7ac65cc07f59ac0d0b010e4ce10bc8a37101 Subproject commit c4a063aba7a39c937592946b45b8f189aaedfbbc

9
csrc/emulator.cc
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@ -97,6 +97,7 @@ int main(int argc, char** argv)
// reset for a few cycles to support pipelined reset // reset for a few cycles to support pipelined reset
tile.Top__io_host_in_valid = LIT<1>(0); tile.Top__io_host_in_valid = LIT<1>(0);
tile.Top__io_host_out_ready = LIT<1>(0); tile.Top__io_host_out_ready = LIT<1>(0);
tile.Top__io_mem_backup_en = LIT<1>(0);
for (int i = 0; i < 10; i++) for (int i = 0; i < 10; i++)
{ {
tile.clock_lo(LIT<1>(1)); tile.clock_lo(LIT<1>(1));
@ -133,9 +134,12 @@ int main(int argc, char** argv)
tile.clock_lo(LIT<1>(0)); tile.clock_lo(LIT<1>(0));
if (tile.Top__io_host_clk_edge.to_bool())
{
htif_phy.tick(tile.Top__io_host_in_ready.lo_word(), htif_phy.tick(tile.Top__io_host_in_ready.lo_word(),
tile.Top__io_host_out_valid.lo_word(), tile.Top__io_host_out_valid.lo_word(),
tile.Top__io_host_out_bits.lo_word()); tile.Top__io_host_out_bits.lo_word());
}
if (tile.Top__io_debug_error_mode.lo_word()) if (tile.Top__io_debug_error_mode.lo_word())
@ -175,8 +179,7 @@ int main(int argc, char** argv)
str[pos] = 0; \ str[pos] = 0; \
fputs(str, vcdfile); \ fputs(str, vcdfile); \
} while(0) } while(0)
dump_disasm(tile.Top_Tile_cpu_dpath__id_reg_inst_shadow.lo_word(), "NDISASM_IF"); dump_disasm(tile.Top_Tile_cpu_dpath__id_inst.lo_word(), "NDISASM_ID");
dump_disasm(tile.Top_Tile_cpu_dpath__id_reg_inst.lo_word(), "NDISASM_ID");
dump_disasm(ex_reg_inst, "NDISASM_EX"); dump_disasm(ex_reg_inst, "NDISASM_EX");
dump_disasm(mem_reg_inst, "NDISASM_MEM"); dump_disasm(mem_reg_inst, "NDISASM_MEM");
@ -196,7 +199,7 @@ int main(int argc, char** argv)
mem_reg_rs1 = tile.Top_Tile_cpu_dpath__ex_reg_rs1.lo_word(); mem_reg_rs1 = tile.Top_Tile_cpu_dpath__ex_reg_rs1.lo_word();
mem_reg_rs2 = tile.Top_Tile_cpu_dpath__ex_reg_rs2.lo_word(); mem_reg_rs2 = tile.Top_Tile_cpu_dpath__ex_reg_rs2.lo_word();
ex_reg_inst = tile.Top_Tile_cpu_dpath__id_reg_inst.lo_word(); ex_reg_inst = tile.Top_Tile_cpu_dpath__id_inst.lo_word();
tile.clock_hi(LIT<1>(0)); tile.clock_hi(LIT<1>(0));
trace_count++; trace_count++;

2
dramsim2

@ -1 +1 @@
Subproject commit d0045b18ce34b350139a43c95c9e432f4c6e43a5 Subproject commit 0b3ee6799a523fc40973dae8dc967ece6f2e3bb9

4
emulator/Makefile
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@ -14,10 +14,10 @@ CXXFLAGS := $(CXXFLAGS) -I$(DRAMSIM2_PATH) -L$(DRAMSIM2_PATH) -ldramsim -Wl,-rpa
DRAMSIM2_LIB := libdramsim.so DRAMSIM2_LIB := libdramsim.so
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project rocket" "run rocket.Top --backend c --noIoDebug --targetDir ../emulator/generated-src" cd $(basedir)/sbt && $(SBT) "project referencechip" "run ReferenceChip.Top --backend c --noIoDebug --targetDir ../emulator/generated-src"
generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project rocket" "run rocket.Top --backend c --debug --vcd --targetDir ../emulator/generated-src-debug" cd $(basedir)/sbt && $(SBT) "project referencechip" "run ReferenceChip.Top --backend c --debug --vcd --targetDir ../emulator/generated-src-debug"
$(MODEL).o: %.o: generated-src/%.cpp $(MODEL).o: %.o: generated-src/%.cpp
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $< $(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<

2
hardfloat

@ -1 +1 @@
Subproject commit eae838000e2f897594f75bfff4a3a74ab993ab2d Subproject commit ada8b49d451176f3d08e3cc08e30ff2659d2803d

2
riscv-rocket

@ -1 +1 @@
Subproject commit 2bc0aa2d52893d01886b5a644852aa7dbaf5a4c8 Subproject commit 12da72a5a6fcb9d33d8f3ceaedc8281c4849fd57

71
src/main/scala/RocketChip.scala
View File

@ -25,7 +25,7 @@ class ReferenceChipBackend extends VerilogBackend
def addMemPin(c: Component) = { def addMemPin(c: Component) = {
for (node <- Component.nodes) { for (node <- Component.nodes) {
if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].inferSeqRead) { if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
val init = Bool(INPUT) val init = Bool(INPUT)
init.setName("init") init.setName("init")
node.inputs += init node.inputs += init
@ -67,27 +67,27 @@ class ReferenceChipBackend extends VerilogBackend
transforms += ((c: Component) => addMemPin(c)) transforms += ((c: Component) => addMemPin(c))
} }
class OuterMemorySystem(ntiles: Int, co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal) class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val tiles = Vec(ntiles) { new ioTileLink() }.flip val tiles = Vec(conf.ntiles) { new ioTileLink() }.flip
val htif = new ioTileLink().flip val htif = new ioTileLink().flip
val mem_backup = new ioMemSerialized val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
val mem = new ioMemPipe val mem = new ioMemPipe
} }
import rocket.Constants._ import rocket.Constants._
val hub = new CoherenceHubBroadcast(NTILES+1, co) val hub = new CoherenceHubBroadcast()(conf.copy(ntiles = conf.ntiles+1))
val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) } val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) } val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf) val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
val mem_serdes = new MemSerdes val mem_serdes = new MemSerdes(htif_width)
for (i <- 0 until NTILES) { for (i <- 0 until conf.ntiles) {
hub.io.tiles(i) <> io.tiles(i) hub.io.tiles(i) <> io.tiles(i)
} }
hub.io.tiles(NTILES) <> io.htif hub.io.tiles(conf.ntiles) <> io.htif
llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd) llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES) llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
@ -116,34 +116,26 @@ class OuterMemorySystem(ntiles: Int, co: CoherencePolicyWithUncached, resetSigna
io.mem_backup <> mem_serdes.io.narrow io.mem_backup <> mem_serdes.io.narrow
} }
class Uncore(htif_width: Int, ntiles: Int, co: CoherencePolicyWithUncached) extends Component class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val debug = new ioDebug() val debug = new ioDebug()
val host = new ioHost(htif_width) val host = new ioHost(htif_width)
val host_clk = Bool(OUTPUT) val mem_backup = new ioMemSerialized(htif_width)
val mem_backup = new ioMemSerialized
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
val mem_backup_clk = Bool(OUTPUT)
val mem = new ioMemPipe val mem = new ioMemPipe
val tiles = Vec(ntiles) { new ioTileLink() }.flip val tiles = Vec(conf.ntiles) { new ioTileLink() }.flip
val htif = Vec(ntiles) { new ioHTIF() }.flip val htif = Vec(conf.ntiles) { new ioHTIF(conf.ntiles) }.flip
val uncore_reset = Bool(OUTPUT)
} }
import rocket.Constants._ val htif = new rocketHTIF(htif_width)
val htif = new rocketHTIF(htif_width, NTILES, co) htif.io.cpu <> io.htif
for (i <- 0 until NTILES) { val outmemsys = new OuterMemorySystem(htif_width)
htif.io.cpu(i) <> io.htif(i)
}
val outmemsys = new OuterMemorySystem(ntiles, co)
outmemsys.io.tiles <> io.tiles outmemsys.io.tiles <> io.tiles
outmemsys.io.htif <> htif.io.mem outmemsys.io.htif <> htif.io.mem
io.mem <> outmemsys.io.mem io.mem <> outmemsys.io.mem
outmemsys.io.mem_backup_en <> io.mem_backup_en outmemsys.io.mem_backup_en <> io.mem_backup_en
io.uncore_reset := htif.io.cpu(NTILES-1).reset
// pad out the HTIF using a divided clock // pad out the HTIF using a divided clock
val hio = (new slowIO(8)) { Bits(width = htif_width+1) } val hio = (new slowIO(8)) { Bits(width = htif_width+1) }
@ -165,13 +157,13 @@ class Uncore(htif_width: Int, ntiles: Int, co: CoherencePolicyWithUncached) exte
htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width) htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
htif.io.host.in.bits := hio.io.in_fast.bits htif.io.host.in.bits := hio.io.in_fast.bits
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready) hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
io.host_clk := hio.io.clk_slow io.host.clk := hio.io.clk_slow
io.host.clk_edge := Reg(io.host.clk && !Reg(io.host.clk))
} }
class ioTop(htif_width: Int) extends Bundle { class ioTop(htif_width: Int) extends Bundle {
val debug = new rocket.ioDebug(); val debug = new rocket.ioDebug();
val host = new rocket.ioHost(htif_width); val host = new rocket.ioHost(htif_width);
val host_clk = Bool(OUTPUT)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
val in_mem_rdy = Bool(OUTPUT) val in_mem_rdy = Bool(OUTPUT)
val in_mem_val = Bool(INPUT) val in_mem_val = Bool(INPUT)
@ -180,10 +172,22 @@ class ioTop(htif_width: Int) extends Bundle {
val mem = new uncore.ioMem val mem = new uncore.ioMem
} }
class ReferenceChipTop extends Component { object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants {
val clkdiv = 8 val NTILES = 1
import rocket.Constants._ val HTIF_WIDTH = 16
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
}
import DummyTopLevelConstants._
class MemDessert extends Component {
val io = new MemDesserIO(HTIF_WIDTH)
val x = new MemDesser(HTIF_WIDTH)
io.narrow <> x.io.narrow
io.wide <> x.io.wide
}
class Top extends Component {
val co = if(ENABLE_SHARING) { val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
else new MSICoherence else new MSICoherence
@ -192,15 +196,19 @@ class ReferenceChipTop extends Component {
else new MICoherence else new MICoherence
} }
implicit val uconf = UncoreConfiguration(NTILES, log2Up(NTILES)+1, co)
val io = new ioTop(HTIF_WIDTH) val io = new ioTop(HTIF_WIDTH)
val uncore = new Uncore(HTIF_WIDTH, NTILES, co) val uncore = new Uncore(HTIF_WIDTH)
var error_mode = Bool(false) var error_mode = Bool(false)
for (i <-0 until NTILES) { for (i <- 0 until uconf.ntiles) {
val hl = uncore.io.htif(i) val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i) val tl = uncore.io.tiles(i)
val tile = new Tile(co, resetSignal = hl.reset)
implicit val rconf = RocketConfiguration(NTILES, co)
val tile = new Tile(resetSignal = hl.reset)
tile.io.host.reset := Reg(Reg(hl.reset)) tile.io.host.reset := Reg(Reg(hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req) tile.io.host.pcr_req <> Queue(hl.pcr_req)
@ -221,7 +229,6 @@ class ReferenceChipTop extends Component {
} }
io.host <> uncore.io.host io.host <> uncore.io.host
io.host_clk := uncore.io.host_clk
uncore.io.mem_backup.resp.valid := io.in_mem_val uncore.io.mem_backup.resp.valid := io.in_mem_val

2
uncore

@ -1 +1 @@
Subproject commit 3603d22434caada0cb84ab46d9e51e79cb644de1 Subproject commit 4c1d5186e13b6782049317747742786850f3778c