riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Use <> instead of := for bi-directional connections

Browse Source
This commit is contained in:
Andrew Waterman
2016-10-04 22:28:56 -07:00
parent 4f6eb38eeb
commit eddf1679f5
10 changed files with 28 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/uncore/agents/Mmio.scala
View File

@ -35,7 +35,7 @@ class MMIOTileLinkManager(implicit p: Parameters)
io.inner.acquire.ready := io.outer.acquire.ready && xact_free
io.outer.acquire.valid := io.inner.acquire.valid && xact_free
io.outer.acquire.bits := io.inner.acquire.bits
io.outer.acquire.bits <> io.inner.acquire.bits
io.outer.acquire.bits.client_xact_id := outer_xact_id
def isLastBeat[T <: TileLinkChannel with HasTileLinkBeatId](in: T): Bool =
@ -56,7 +56,7 @@ class MMIOTileLinkManager(implicit p: Parameters)
clearPendingBitOnGnt(io.inner.grant)
when (io.outer.acquire.fire() && isLastBeat(io.outer.acquire.bits)) {
xact_buffer(outer_xact_id) := io.iacq()
xact_buffer(outer_xact_id) <> io.iacq()
}
when (multibeat_start) { xact_multibeat := Bool(true) }
@ -65,7 +65,7 @@ class MMIOTileLinkManager(implicit p: Parameters)
val gnt_xact = xact_buffer(io.ognt().client_xact_id)
io.outer.grant.ready := io.inner.grant.ready
io.inner.grant.valid := io.outer.grant.valid
io.inner.grant.bits := io.outer.grant.bits
io.inner.grant.bits <> io.outer.grant.bits
io.inner.grant.bits.client_id := gnt_xact.client_id
io.inner.grant.bits.client_xact_id := gnt_xact.client_xact_id
io.inner.grant.bits.manager_xact_id := io.ognt().client_xact_id

4
src/main/scala/uncore/tilelink/Network.scala
View File

@ -157,12 +157,12 @@ class FinishUnit(srcId: Int = 0, outstanding: Int = 2)(implicit p: Parameters) e
}
val q = Module(new FinishQueue(outstanding))
q.io.enq.valid := io.grant.fire() && g.requiresAck() && (!g.hasMultibeatData() || done)
q.io.enq.bits := g.makeFinish()
q.io.enq.bits <> g.makeFinish()
q.io.enq.bits.manager_id := io.grant.bits.header.src
io.finish.bits.header.src := UInt(srcId)
io.finish.bits.header.dst := q.io.deq.bits.manager_id
io.finish.bits.payload := q.io.deq.bits
io.finish.bits.payload <> q.io.deq.bits
io.finish.valid := q.io.deq.valid
q.io.deq.ready := io.finish.ready

10
src/main/scala/uncore/tilelink2/Bundles.scala
View File

@ -211,11 +211,11 @@ object TLBundleSnoop
{
def apply(x: TLBundle) = {
val out = Wire(new TLBundleSnoop(x.params))
out.a := IrrevocableSnoop(x.a)
out.b := IrrevocableSnoop(x.b)
out.c := IrrevocableSnoop(x.c)
out.d := IrrevocableSnoop(x.d)
out.e := IrrevocableSnoop(x.e)
out.a <> IrrevocableSnoop(x.a)
out.b <> IrrevocableSnoop(x.b)
out.c <> IrrevocableSnoop(x.c)
out.d <> IrrevocableSnoop(x.d)
out.e <> IrrevocableSnoop(x.e)
out
}
}

20
src/main/scala/uncore/tilelink2/Crossing.scala
View File

@ -21,13 +21,13 @@ class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule
val bce = edgeIn.manager.anySupportAcquire && edgeIn.client.anySupportProbe
val depth = edgeOut.manager.depth
out.a := ToAsyncBundle(in.a, depth, sync)
in.d := FromAsyncBundle(out.d, sync)
out.a <> ToAsyncBundle(in.a, depth, sync)
in.d <> FromAsyncBundle(out.d, sync)
if (bce) {
in.b := FromAsyncBundle(out.b, sync)
out.c := ToAsyncBundle(in.c, depth, sync)
out.e := ToAsyncBundle(in.e, depth, sync)
in.b <> FromAsyncBundle(out.b, sync)
out.c <> ToAsyncBundle(in.c, depth, sync)
out.e <> ToAsyncBundle(in.e, depth, sync)
} else {
in.b.valid := Bool(false)
in.c.ready := Bool(true)
@ -53,13 +53,13 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
val bce = edgeOut.manager.anySupportAcquire && edgeOut.client.anySupportProbe
out.a := FromAsyncBundle(in.a, sync)
in.d := ToAsyncBundle(out.d, depth, sync)
out.a <> FromAsyncBundle(in.a, sync)
in.d <> ToAsyncBundle(out.d, depth, sync)
if (bce) {
in.b := ToAsyncBundle(out.b, depth, sync)
out.c := FromAsyncBundle(in.c, sync)
out.e := FromAsyncBundle(in.e, sync)
in.b <> ToAsyncBundle(out.b, depth, sync)
out.c <> FromAsyncBundle(in.c, sync)
out.e <> FromAsyncBundle(in.e, sync)
} else {
in.b.widx := UInt(0)
in.c.ridx := UInt(0)