diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index bb933227..22d26ca1 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -146,7 +146,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle]( // connect coreplex-internal interrupts to tiles for ((tile, i) <- (uncoreTileIOs zipWithIndex)) { - tile.interrupts := io.clint(i) + tile.interrupts <> io.clint(i) tile.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M')) tile.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S'))) tile.interrupts.debug := debugModule.io.debugInterrupts(i) diff --git a/src/main/scala/rocket/csr.scala b/src/main/scala/rocket/csr.scala index 1aeaca94..c25cd682 100644 --- a/src/main/scala/rocket/csr.scala +++ b/src/main/scala/rocket/csr.scala @@ -623,7 +623,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) } } - reg_mip := io.interrupts + reg_mip <> io.interrupts reg_dcsr.debugint := io.interrupts.debug if (!usingVM) { diff --git a/src/main/scala/rocket/dcache.scala b/src/main/scala/rocket/dcache.scala index fb9ba01f..1ec565c2 100644 --- a/src/main/scala/rocket/dcache.scala +++ b/src/main/scala/rocket/dcache.scala @@ -431,7 +431,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { // cached response io.cpu.resp.valid := s2_valid_hit - io.cpu.resp.bits := s2_req + io.cpu.resp.bits <> s2_req io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false io.cpu.ordered := !(s1_valid || s2_valid || cached_grant_wait || uncachedInFlight.asUInt.orR) diff --git a/src/main/scala/rocket/multiplier.scala b/src/main/scala/rocket/multiplier.scala index 90ed3f08..f3b63b29 100644 --- a/src/main/scala/rocket/multiplier.scala +++ b/src/main/scala/rocket/multiplier.scala @@ -148,7 +148,7 @@ class MulDiv(cfg: MulDivConfig, width: Int, nXpr: Int = 32) extends Module { req := io.req.bits } - io.resp.bits := req + io.resp.bits <> req io.resp.bits.data := Mux(halfWidth(req), Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0)) io.resp.valid := state === s_done io.req.ready := state === s_ready diff --git a/src/main/scala/rocket/tlb.scala b/src/main/scala/rocket/tlb.scala index cf9b5bb2..8bb1e666 100644 --- a/src/main/scala/rocket/tlb.scala +++ b/src/main/scala/rocket/tlb.scala @@ -134,7 +134,7 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters { io.resp.ppn := Mux1H(hitsVec, ppns :+ passthrough_ppn) io.ptw.req.valid := state === s_request - io.ptw.req.bits := io.ptw.status + io.ptw.req.bits <> io.ptw.status io.ptw.req.bits.addr := r_refill_tag io.ptw.req.bits.store := r_req.store io.ptw.req.bits.fetch := r_req.instruction diff --git a/src/main/scala/rocketchip/DebugTransport.scala b/src/main/scala/rocketchip/DebugTransport.scala index 74078853..e8e5b017 100644 --- a/src/main/scala/rocketchip/DebugTransport.scala +++ b/src/main/scala/rocketchip/DebugTransport.scala @@ -55,7 +55,7 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters) val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width)) - jtag_dtm.io.jtag := io.jtag + jtag_dtm.io.jtag <> io.jtag val dtm_req = Wire(new DecoupledIO(UInt(width = req_width))) val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width))) @@ -74,8 +74,8 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters) dtm_resp.bits := io_debug_bus.resp.bits.asUInt io_debug_bus.resp.ready := dtm_resp.ready - dtm_req := jtag_dtm.io.dtm_req - jtag_dtm.io.dtm_resp := dtm_resp + dtm_req <> jtag_dtm.io.dtm_req + jtag_dtm.io.dtm_resp <> dtm_resp } class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox { diff --git a/src/main/scala/uncore/agents/Mmio.scala b/src/main/scala/uncore/agents/Mmio.scala index a3b2ab03..08ccc4d3 100644 --- a/src/main/scala/uncore/agents/Mmio.scala +++ b/src/main/scala/uncore/agents/Mmio.scala @@ -35,7 +35,7 @@ class MMIOTileLinkManager(implicit p: Parameters) io.inner.acquire.ready := io.outer.acquire.ready && xact_free io.outer.acquire.valid := io.inner.acquire.valid && xact_free - io.outer.acquire.bits := io.inner.acquire.bits + io.outer.acquire.bits <> io.inner.acquire.bits io.outer.acquire.bits.client_xact_id := outer_xact_id def isLastBeat[T <: TileLinkChannel with HasTileLinkBeatId](in: T): Bool = @@ -56,7 +56,7 @@ class MMIOTileLinkManager(implicit p: Parameters) clearPendingBitOnGnt(io.inner.grant) when (io.outer.acquire.fire() && isLastBeat(io.outer.acquire.bits)) { - xact_buffer(outer_xact_id) := io.iacq() + xact_buffer(outer_xact_id) <> io.iacq() } when (multibeat_start) { xact_multibeat := Bool(true) } @@ -65,7 +65,7 @@ class MMIOTileLinkManager(implicit p: Parameters) val gnt_xact = xact_buffer(io.ognt().client_xact_id) io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid - io.inner.grant.bits := io.outer.grant.bits + io.inner.grant.bits <> io.outer.grant.bits io.inner.grant.bits.client_id := gnt_xact.client_id io.inner.grant.bits.client_xact_id := gnt_xact.client_xact_id io.inner.grant.bits.manager_xact_id := io.ognt().client_xact_id diff --git a/src/main/scala/uncore/tilelink/Network.scala b/src/main/scala/uncore/tilelink/Network.scala index 1a572e78..2a5fd8ab 100644 --- a/src/main/scala/uncore/tilelink/Network.scala +++ b/src/main/scala/uncore/tilelink/Network.scala @@ -157,12 +157,12 @@ class FinishUnit(srcId: Int = 0, outstanding: Int = 2)(implicit p: Parameters) e } val q = Module(new FinishQueue(outstanding)) q.io.enq.valid := io.grant.fire() && g.requiresAck() && (!g.hasMultibeatData() || done) - q.io.enq.bits := g.makeFinish() + q.io.enq.bits <> g.makeFinish() q.io.enq.bits.manager_id := io.grant.bits.header.src io.finish.bits.header.src := UInt(srcId) io.finish.bits.header.dst := q.io.deq.bits.manager_id - io.finish.bits.payload := q.io.deq.bits + io.finish.bits.payload <> q.io.deq.bits io.finish.valid := q.io.deq.valid q.io.deq.ready := io.finish.ready diff --git a/src/main/scala/uncore/tilelink2/Bundles.scala b/src/main/scala/uncore/tilelink2/Bundles.scala index 45fdd960..32deff95 100644 --- a/src/main/scala/uncore/tilelink2/Bundles.scala +++ b/src/main/scala/uncore/tilelink2/Bundles.scala @@ -211,11 +211,11 @@ object TLBundleSnoop { def apply(x: TLBundle) = { val out = Wire(new TLBundleSnoop(x.params)) - out.a := IrrevocableSnoop(x.a) - out.b := IrrevocableSnoop(x.b) - out.c := IrrevocableSnoop(x.c) - out.d := IrrevocableSnoop(x.d) - out.e := IrrevocableSnoop(x.e) + out.a <> IrrevocableSnoop(x.a) + out.b <> IrrevocableSnoop(x.b) + out.c <> IrrevocableSnoop(x.c) + out.d <> IrrevocableSnoop(x.d) + out.e <> IrrevocableSnoop(x.e) out } } diff --git a/src/main/scala/uncore/tilelink2/Crossing.scala b/src/main/scala/uncore/tilelink2/Crossing.scala index 92b0795c..394fbcb1 100644 --- a/src/main/scala/uncore/tilelink2/Crossing.scala +++ b/src/main/scala/uncore/tilelink2/Crossing.scala @@ -21,13 +21,13 @@ class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule val bce = edgeIn.manager.anySupportAcquire && edgeIn.client.anySupportProbe val depth = edgeOut.manager.depth - out.a := ToAsyncBundle(in.a, depth, sync) - in.d := FromAsyncBundle(out.d, sync) + out.a <> ToAsyncBundle(in.a, depth, sync) + in.d <> FromAsyncBundle(out.d, sync) if (bce) { - in.b := FromAsyncBundle(out.b, sync) - out.c := ToAsyncBundle(in.c, depth, sync) - out.e := ToAsyncBundle(in.e, depth, sync) + in.b <> FromAsyncBundle(out.b, sync) + out.c <> ToAsyncBundle(in.c, depth, sync) + out.e <> ToAsyncBundle(in.e, depth, sync) } else { in.b.valid := Bool(false) in.c.ready := Bool(true) @@ -53,13 +53,13 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) => val bce = edgeOut.manager.anySupportAcquire && edgeOut.client.anySupportProbe - out.a := FromAsyncBundle(in.a, sync) - in.d := ToAsyncBundle(out.d, depth, sync) + out.a <> FromAsyncBundle(in.a, sync) + in.d <> ToAsyncBundle(out.d, depth, sync) if (bce) { - in.b := ToAsyncBundle(out.b, depth, sync) - out.c := FromAsyncBundle(in.c, sync) - out.e := FromAsyncBundle(in.e, sync) + in.b <> ToAsyncBundle(out.b, depth, sync) + out.c <> FromAsyncBundle(in.c, sync) + out.e <> FromAsyncBundle(in.e, sync) } else { in.b.widx := UInt(0) in.c.ridx := UInt(0)