Use <> instead of := for bi-directional connections

src/main/scala/rocket/csr.scala

@@ -623,7 +623,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     }
   }
 
-  reg_mip := io.interrupts
+  reg_mip <> io.interrupts
   reg_dcsr.debugint := io.interrupts.debug
 
   if (!usingVM) {

src/main/scala/rocket/dcache.scala

@@ -431,7 +431,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
 
   // cached response
   io.cpu.resp.valid := s2_valid_hit
-  io.cpu.resp.bits := s2_req
+  io.cpu.resp.bits <> s2_req
   io.cpu.resp.bits.has_data := s2_read
   io.cpu.resp.bits.replay := false
   io.cpu.ordered := !(s1_valid || s2_valid || cached_grant_wait || uncachedInFlight.asUInt.orR)

src/main/scala/rocket/multiplier.scala

@@ -148,7 +148,7 @@ class MulDiv(cfg: MulDivConfig, width: Int, nXpr: Int = 32) extends Module {
     req := io.req.bits
   }
 
-  io.resp.bits := req
+  io.resp.bits <> req
   io.resp.bits.data := Mux(halfWidth(req), Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
   io.resp.valid := state === s_done
   io.req.ready := state === s_ready

src/main/scala/rocket/tlb.scala

@@ -134,7 +134,7 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
   io.resp.ppn := Mux1H(hitsVec, ppns :+ passthrough_ppn)
 
   io.ptw.req.valid := state === s_request
-  io.ptw.req.bits := io.ptw.status
+  io.ptw.req.bits <> io.ptw.status
   io.ptw.req.bits.addr := r_refill_tag
   io.ptw.req.bits.store := r_req.store
   io.ptw.req.bits.fetch := r_req.instruction