riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge remote-tracking branch 'origin' into testharness-refactor

Browse Source
This commit is contained in:
Henry Cook
2016-09-20 13:03:21 -07:00
parent b97a0947a9 74fc7c5803
commit ed91e9a89b
30 changed files with 335 additions and 174 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/main/scala/rocketchip/BaseTop.scala
View File

@ -27,6 +27,10 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val pBusMasters = new RangeManager
val pDevices = new ResourceManager[AddrMapEntry]
// Add a peripheral bus
val peripheryBus = LazyModule(new TLXbar)
lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
lazy val c = CoreplexConfig(
nTiles = q(NTiles),
nExtInterrupts = pInterrupts.sum,
@ -36,16 +40,14 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
hasExtMMIOPort = true
)
lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get)
lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers)
private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get)
lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get, peripheryManagers)
implicit val p = qWithMap.alterPartial({
case ConfigString => genConfigString
case NCoreplexExtClients => pBusMasters.sum})
// Add a peripheral bus
val peripheryBus = LazyModule(new TLXbar)
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
peripheryBus.node := TLBuffer(TLWidthWidget(TLHintHandler(legacy.node), legacy.tlDataBytes))
@ -55,7 +57,7 @@ class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBun
val success = Bool(OUTPUT)
}
class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
val outer: L = l
val coreplex = p(BuildCoreplex)(p, outer.c)
@ -72,7 +74,12 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
val name = entry.name
val start = entry.region.start
val end = entry.region.start + entry.region.size - 1
println(f"\t$name%s $start%x - $end%x")
val prot = entry.region.attr.prot
val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
(if ((prot & AddrMapProt.W) > 0) "W" else "") +
(if ((prot & AddrMapProt.X) > 0) "X" else "")
val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
}
println("Generated Configuration String")

1
src/main/scala/rocketchip/ExampleTop.scala
View File

@ -21,6 +21,7 @@ class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
with HardwiredResetVector
/** Example Top with TestRAM */
class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)

25
src/main/scala/rocketchip/Periphery.scala
View File

@ -289,10 +289,6 @@ trait PeripheryCoreplexLocalInterrupter extends LazyModule with HasPeripheryPara
val clint = LazyModule(new CoreplexLocalInterrupter(clintConfig)(innerMMIOParams))
// The periphery bus is 32-bit, so we may need to adapt its width to XLen
clint.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
// TL1 legacy
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("clint", MemRange(clintConfig.address, clintConfig.size, MemAttr(AddrMapProt.RW))))
}
trait PeripheryCoreplexLocalInterrupterBundle {
@ -315,12 +311,10 @@ trait PeripheryBootROM extends LazyModule {
implicit val p: Parameters
val peripheryBus: TLXbar
val rom = LazyModule(new TLROM(0x1000, 0x1000, GenerateBootROM(p)))
val address = 0x1000
val size = 0x1000
val rom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address)) { override def name = "bootrom" })
rom.node := TLFragmenter(peripheryBus.node, 4, 256)
// TL1 legacy address map
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("bootrom", MemRange(0x1000, 4096, MemAttr(AddrMapProt.RX))))
}
trait PeripheryBootROMBundle {
@ -342,12 +336,8 @@ trait PeripheryTestRAM extends LazyModule {
val ramBase = 0x52000000
val ramSize = 0x1000
val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1)))
val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1)) { override def name = "testram" })
sram.node := TLFragmenter(peripheryBus.node, 4, 256)
// TL1 legacy address map
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("testram", MemRange(ramBase, ramSize, MemAttr(AddrMapProt.RW))))
}
trait PeripheryTestRAMBundle {
@ -377,3 +367,10 @@ trait PeripheryTestBusMasterModule {
implicit val p: Parameters
val outer: PeripheryTestBusMaster
}
/////
trait HardwiredResetVector {
val coreplex: Coreplex
coreplex.io.resetVector := UInt(0x1000) // boot ROM
}

43
src/main/scala/rocketchip/Utils.scala
View File

@ -8,6 +8,7 @@ import uncore.devices._
import rocket._
import rocket.Util._
import coreplex._
import uncore.tilelink2._
import java.nio.file.{Files, Paths}
import java.nio.{ByteBuffer, ByteOrder}
@ -51,7 +52,7 @@ class GlobalVariable[T] {
}
object GenerateGlobalAddrMap {
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry]) = {
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
lazy val intIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
@ -64,8 +65,26 @@ object GenerateGlobalAddrMap {
new AddrMap(entries)
}
lazy val tl2AddrMap = new AddrMap(pDevicesEntries, collapse = true)
lazy val extIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: p(ExtMMIOPorts), collapse = true)
lazy val tl2Devices = peripheryManagers.map { manager =>
val cacheable = manager.regionType match {
case RegionType.CACHED => true
case RegionType.TRACKED => true
case _ => false
}
val attr = MemAttr(
(if (manager.supportsGet) AddrMapProt.R else 0) |
(if (manager.supportsPutFull) AddrMapProt.W else 0) |
(if (manager.executable) AddrMapProt.X else 0), cacheable)
val multi = manager.address.size > 1
manager.address.zipWithIndex.map { case (address, i) =>
require (address.contiguous) // TL1 needs this
val name = manager.name + (if (multi) ".%d".format(i) else "")
AddrMapEntry(name, MemRange(address.base, address.mask+1, attr))
}
}.flatten
lazy val tl2AddrMap = new AddrMap(tl2Devices, collapse = true)
lazy val extIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
val memBase = 0x80000000L
val memSize = p(ExtMemSize)
@ -80,7 +99,7 @@ object GenerateGlobalAddrMap {
}
object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:int:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:ext:TL2:clint").start)
@ -136,33 +155,27 @@ object GenerateConfigString {
}
res append "};\n"
pDevicesEntries foreach { entry =>
val region = addrMap("io:ext:TL2:" + entry.name)
val region = addrMap("io:ext:" + entry.name)
res append s"${entry.name} {\n"
res append s" addr 0x${region.start.toString(16)};\n"
res append s" size 0x${region.size.toString(16)}; \n"
res append "}\n"
}
peripheryManagers.foreach { manager => res append manager.dts }
res append '\u0000'
res.toString
}
}
object GenerateBootROM {
def apply(p: Parameters) = {
def apply(p: Parameters, address: BigInt) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata)
rom.order(ByteOrder.LITTLE_ENDIAN)
// for now, have the reset vector jump straight to memory
val memBase = (
if (p(GlobalAddrMap) contains "mem") p(GlobalAddrMap)("mem")
else p(GlobalAddrMap)("io:int:dmem0")
).start
val resetToMemDist = memBase - p(ResetVector)
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
val configStringAddr = p(ResetVector).toInt + rom.capacity
require(address == address.toInt)
val configStringAddr = address.toInt + rom.capacity
require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr)