riscv/rocket-chip
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Merge remote-tracking branch 'origin' into testharness-refactor

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This commit is contained in:
Henry Cook
2016-09-20 13:03:21 -07:00
parent b97a0947a9 74fc7c5803
commit ed91e9a89b
30 changed files with 335 additions and 174 deletions
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2
src/main/scala/coreplex/Coreplex.scala
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@ -58,6 +58,7 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
val debug = new DebugBusIO()(p).flip
val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
val success = Bool(OUTPUT)
val resetVector = UInt(INPUT, p(XLen))
}
val io = new CoreplexIO
@ -155,6 +156,7 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)
tile.io.hartid := i
tile.io.resetVector := io.resetVector
}
val tileSlavePorts = (0 until tc.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)