riscv/rocket-chip
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eliminate D$ probe->WB critical path

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This commit is contained in:
Andrew Waterman
2012-10-04 09:05:14 -07:00
parent e909093f37
commit ed8cc4a1cf
1 changed files with 3 additions and 2 deletions
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5
rocket/src/main/scala/nbdcache.scala
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@@ -238,7 +238,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
when (abort) { state := s_wb_req } when (abort) { state := s_wb_req }
} }
when (state === s_wb_req) { when (state === s_wb_req) {
when (io.probe_writeback.valid && idx_match) { state := s_refill_req } when (io.probe_writeback.valid && io.probe_writeback.bits && idx_match) { state := s_refill_req }
.elsewhen (io.wb_req.ready) { state := s_wb_resp } .elsewhen (io.wb_req.ready) { state := s_wb_resp }
} }
@@ -366,7 +366,8 @@ class MSHRFile(co: CoherencePolicy) extends Component {
mshr.io.wb_req <> wb_req_arb.io.in(i) mshr.io.wb_req <> wb_req_arb.io.in(i)
mshr.io.replay <> replay_arb.io.in(i) mshr.io.replay <> replay_arb.io.in(i)
mshr.io.probe_refill.valid := io.probe.valid && tag_match mshr.io.probe_refill.valid := io.probe.valid && tag_match
mshr.io.probe_writeback.valid := io.probe.valid && wb_probe_match mshr.io.probe_writeback.valid := io.probe.valid
mshr.io.probe_writeback.bits := wb_probe_match
mshr.io.mem_abort <> io.mem_abort mshr.io.mem_abort <> io.mem_abort
mshr.io.mem_rep <> io.mem_rep mshr.io.mem_rep <> io.mem_rep