Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
This commit is contained in:
Andrew Waterman
195
csrc/emulator.cc
195
csrc/emulator.cc
@ -1,15 +1,9 @@
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// See LICENSE for license details.
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#ifndef VERILATOR
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#include "emulator.h"
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#else
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#include "verilated.h"
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#if VM_TRACE
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#include "verilated_vcd_c.h"
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#endif
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#endif
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#include "mm.h"
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#include "mm_dramsim2.h"
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#include <fesvr/dtm.h>
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#include <iostream>
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#include <fcntl.h>
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@ -18,13 +12,7 @@
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#include <stdlib.h>
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#include <unistd.h>
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#define MEM_SIZE_BITS 3
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#define MEM_LEN_BITS 8
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#define MEM_RESP_BITS 2
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#include "emulator_type.h"
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static dtm_t* dtm;
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extern dtm_t* dtm;
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static uint64_t trace_count = 0;
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bool verbose;
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@ -38,18 +26,19 @@ double sc_time_stamp()
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return trace_count;
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}
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extern "C" int vpi_get_vlog_info(void* arg)
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{
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return 0;
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}
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int main(int argc, char** argv)
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{
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unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
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uint64_t max_cycles = -1;
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uint64_t start = 0;
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int ret = 0;
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const char* loadmem = NULL;
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FILE *vcdfile = NULL;
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bool dramsim2 = false;
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bool print_cycles = false;
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uint64_t memsz_mb = MEM_SIZE / (1024*1024);
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mm_t *mm[N_MEM_CHANNELS];
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for (int i = 1; i < argc; i++)
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{
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@ -59,18 +48,12 @@ int main(int argc, char** argv)
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vcdfile = strcmp(filename, "-") == 0 ? stdout : fopen(filename, "w");
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if (!vcdfile)
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abort();
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} else if (arg.substr(0, 9) == "+memsize=")
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memsz_mb = atoll(argv[i]+9);
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else if (arg.substr(0, 2) == "-s")
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} else if (arg.substr(0, 2) == "-s")
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random_seed = atoi(argv[i]+2);
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else if (arg == "+dramsim")
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dramsim2 = true;
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else if (arg == "+verbose")
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verbose = true;
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else if (arg.substr(0, 12) == "+max-cycles=")
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max_cycles = atoll(argv[i]+12);
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else if (arg.substr(0, 9) == "+loadmem=")
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loadmem = argv[i]+9;
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else if (arg.substr(0, 7) == "+start=")
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start = atoll(argv[i]+7);
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else if (arg.substr(0, 12) == "+cycle-count")
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@ -80,12 +63,8 @@ int main(int argc, char** argv)
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srand(random_seed);
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srand48(random_seed);
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#ifndef VERILATOR
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Top_t tile;
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tile.init(random_seed);
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#else
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Verilated::randReset(2);
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VTop tile;
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VTestHarness tile;
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#if VM_TRACE
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Verilated::traceEverOn(true); // Verilator must compute traced signals
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@ -96,30 +75,6 @@ int main(int argc, char** argv)
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tfp->open("");
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}
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#endif
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#endif
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uint64_t mem_width = MEM_DATA_BITS / 8;
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// Instantiate and initialize main memory
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for (int i = 0; i < N_MEM_CHANNELS; i++) {
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mm[i] = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
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try {
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mm[i]->init(memsz_mb*1024*1024 / N_MEM_CHANNELS, mem_width, CACHE_BLOCK_BYTES);
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} catch (const std::bad_alloc& e) {
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fprintf(stderr,
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"Failed to allocate %ld bytes (%ld MiB) of memory\n"
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"Set smaller amount of memory using +memsize=<N> (in MiB)\n",
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memsz_mb*1024*1024, memsz_mb);
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exit(-1);
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}
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}
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if (loadmem) {
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void *mems[N_MEM_CHANNELS];
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for (int i = 0; i < N_MEM_CHANNELS; i++)
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mems[i] = mm[i]->get_data();
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load_mem(mems, loadmem, CACHE_BLOCK_BYTES, N_MEM_CHANNELS);
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}
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dtm = new dtm_t(std::vector<std::string>(argv + 1, argv + argc));
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@ -127,155 +82,35 @@ int main(int argc, char** argv)
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// reset for several cycles to handle pipelined reset
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for (int i = 0; i < 10; i++) {
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#ifndef VERILATOR
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tile.clock_lo(LIT<1>(1));
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tile.clock_hi(LIT<1>(1));
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#else
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tile.reset = 1;
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tile.clk = 0;
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tile.eval();
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tile.clk = 1;
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tile.eval();
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tile.reset = 0;
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#endif
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}
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bool_t *mem_ar_valid[N_MEM_CHANNELS];
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bool_t *mem_ar_ready[N_MEM_CHANNELS];
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mem_addr_t *mem_ar_bits_addr[N_MEM_CHANNELS];
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mem_id_t *mem_ar_bits_id[N_MEM_CHANNELS];
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mem_size_t *mem_ar_bits_size[N_MEM_CHANNELS];
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mem_len_t *mem_ar_bits_len[N_MEM_CHANNELS];
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bool_t *mem_aw_valid[N_MEM_CHANNELS];
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bool_t *mem_aw_ready[N_MEM_CHANNELS];
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mem_addr_t *mem_aw_bits_addr[N_MEM_CHANNELS];
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mem_id_t *mem_aw_bits_id[N_MEM_CHANNELS];
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mem_size_t *mem_aw_bits_size[N_MEM_CHANNELS];
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mem_len_t *mem_aw_bits_len[N_MEM_CHANNELS];
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bool_t *mem_w_valid[N_MEM_CHANNELS];
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bool_t *mem_w_ready[N_MEM_CHANNELS];
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mem_data_t *mem_w_bits_data[N_MEM_CHANNELS];
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mem_strb_t *mem_w_bits_strb[N_MEM_CHANNELS];
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bool_t *mem_w_bits_last[N_MEM_CHANNELS];
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bool_t *mem_b_valid[N_MEM_CHANNELS];
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bool_t *mem_b_ready[N_MEM_CHANNELS];
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mem_resp_t *mem_b_bits_resp[N_MEM_CHANNELS];
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mem_id_t *mem_b_bits_id[N_MEM_CHANNELS];
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bool_t *mem_r_valid[N_MEM_CHANNELS];
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bool_t *mem_r_ready[N_MEM_CHANNELS];
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mem_resp_t *mem_r_bits_resp[N_MEM_CHANNELS];
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mem_id_t *mem_r_bits_id[N_MEM_CHANNELS];
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mem_data_t *mem_r_bits_data[N_MEM_CHANNELS];
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bool_t *mem_r_bits_last[N_MEM_CHANNELS];
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#include TBFRAG
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while (!dtm->done() && trace_count < max_cycles && ret == 0)
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{
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for (int i = 0; i < N_MEM_CHANNELS; i++) {
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value(mem_ar_ready[i]) = mm[i]->ar_ready();
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value(mem_aw_ready[i]) = mm[i]->aw_ready();
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value(mem_w_ready[i]) = mm[i]->w_ready();
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value(mem_b_valid[i]) = mm[i]->b_valid();
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value(mem_b_bits_resp[i]) = mm[i]->b_resp();
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value(mem_b_bits_id[i]) = mm[i]->b_id();
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value(mem_r_valid[i]) = mm[i]->r_valid();
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value(mem_r_bits_resp[i]) = mm[i]->r_resp();
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value(mem_r_bits_id[i]) = mm[i]->r_id();
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value(mem_r_bits_last[i]) = mm[i]->r_last();
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memcpy(values(mem_r_bits_data[i]), mm[i]->r_data(), mem_width);
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}
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value(field(io_debug_resp_ready)) = dtm->resp_ready();
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value(field(io_debug_req_valid)) = dtm->req_valid();
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value(field(io_debug_req_bits_addr)) = dtm->req_bits().addr;
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value(field(io_debug_req_bits_op)) = dtm->req_bits().op;
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value(field(io_debug_req_bits_data)) = dtm->req_bits().data;
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try {
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#ifndef VERILATOR
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tile.clock_lo(LIT<1>(0));
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#else
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tile.clk = 0;
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tile.eval();
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// make sure we dump on cycle 0 to get dump_init
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while (!dtm->done() && !tile.io_success && trace_count < max_cycles) {
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tile.clk = 0;
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tile.eval();
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#if VM_TRACE
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if (tfp && (trace_count == 0 || trace_count >= start))
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tfp->dump(trace_count * 2);
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bool dump = tfp && trace_count >= start;
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if (dump)
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tfp->dump(trace_count * 2);
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#endif
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#endif
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} catch (std::runtime_error& e) {
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max_cycles = trace_count; // terminate cleanly after this cycle
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ret = 1;
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std::cerr << e.what() << std::endl;
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}
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dtm_t::resp debug_resp_bits;
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debug_resp_bits.resp = value(field(io_debug_resp_bits_resp));
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debug_resp_bits.data = value(field(io_debug_resp_bits_data));
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dtm->tick(
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value(field(io_debug_req_ready)),
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value(field(io_debug_resp_valid)),
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debug_resp_bits
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);
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for (int i = 0; i < N_MEM_CHANNELS; i++) {
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mm[i]->tick(
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value(mem_ar_valid[i]),
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value(mem_ar_bits_addr[i]) - MEM_BASE,
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value(mem_ar_bits_id[i]),
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value(mem_ar_bits_size[i]),
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value(mem_ar_bits_len[i]),
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value(mem_aw_valid[i]),
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value(mem_aw_bits_addr[i]) - MEM_BASE,
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value(mem_aw_bits_id[i]),
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value(mem_aw_bits_size[i]),
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value(mem_aw_bits_len[i]),
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value(mem_w_valid[i]),
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value(mem_w_bits_strb[i]),
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values(mem_w_bits_data[i]),
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value(mem_w_bits_last[i]),
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value(mem_r_ready[i]),
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value(mem_b_ready[i])
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);
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}
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#ifndef VERILATOR
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if (verbose && trace_count >= start)
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tile.print(stderr);
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// make sure we dump on cycle 0 to get dump_init
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if (vcdfile && (trace_count == 0 || trace_count >= start))
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tile.dump(vcdfile, trace_count);
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tile.clock_hi(LIT<1>(0));
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#else
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tile.clk = 1;
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tile.eval();
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#if VM_TRACE
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if (tfp && (trace_count == 0 || trace_count >= start))
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if (dump)
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tfp->dump(trace_count * 2 + 1);
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#endif
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#endif
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trace_count++;
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}
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#ifdef VERILATOR
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#if VM_TRACE
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if (tfp)
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tfp->close();
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#endif
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#endif
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if (vcdfile)
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