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plic: support a configurable number of interrupt register stages

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This commit is contained in:
Wesley W. Terpstra 2017-09-06 14:21:09 -07:00
parent 9b55063de6
commit ed70b243bd
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/devices/tilelink/Plic.scala
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@ -52,7 +52,7 @@ object PLICConsts
require(hartBase >= enableBase(maxHarts)) require(hartBase >= enableBase(maxHarts))
} }
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7) case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0)
{ {
require (maxPriorities >= 0) require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size-1) def address = AddressSet(baseAddress, PLICConsts.size-1)
@ -166,7 +166,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
val (maxPri, maxDev) = findMax(effectivePriority) val (maxPri, maxDev) = findMax(effectivePriority)
maxDevs(hart) := maxDev maxDevs(hart) := maxDev
harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart)) harts(hart) := ShiftRegister(Reg(next = maxPri) > Cat(UInt(1), threshold(hart)), params.intStages)
} }
def priorityRegField(x: UInt) = if (nPriorities > 0) RegField(32, x) else RegField.r(32, x) def priorityRegField(x: UInt) = if (nPriorities > 0) RegField(32, x) else RegField.r(32, x)