From ed70b243bde723e205220762955774fa28bf02ff Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 6 Sep 2017 14:21:09 -0700 Subject: [PATCH] plic: support a configurable number of interrupt register stages --- src/main/scala/devices/tilelink/Plic.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index 5581352e..94b0e186 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -52,7 +52,7 @@ object PLICConsts require(hartBase >= enableBase(maxHarts)) } -case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7) +case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size-1) @@ -166,7 +166,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule val (maxPri, maxDev) = findMax(effectivePriority) maxDevs(hart) := maxDev - harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart)) + harts(hart) := ShiftRegister(Reg(next = maxPri) > Cat(UInt(1), threshold(hart)), params.intStages) } def priorityRegField(x: UInt) = if (nPriorities > 0) RegField(32, x) else RegField.r(32, x)