riscv/rocket-chip
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crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain

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This commit is contained in:
Wesley W. Terpstra
2016-09-07 13:55:22 -07:00
parent 33a05786db
commit ecdfb528c5
4 changed files with 91 additions and 97 deletions
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27
src/main/scala/rocketchip/DebugTransport.scala
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@ -86,19 +86,19 @@ class JtagDTMWithSync(implicit val p: Parameters) extends Module {
} else {
val req_sync = Module (new AsyncMailbox())
val resp_sync = Module (new AsyncMailbox())
req_sync.io.enq := jtag_dtm.io.dtm_req
req_sync.io.enq_clock.get := io.jtag.TCK
req_sync.io.enq_reset.get := io.jtag.TRST
req_sync.io.deq_clock.get := clock
req_sync.io.deq_reset.get := reset
dtm_req := req_sync.io.deq
req_sync.io.enq := jtag_dtm.io.dtm_req
req_sync.io.enq_clock := io.jtag.TCK
req_sync.io.enq_reset := io.jtag.TRST
req_sync.io.deq_clock := clock
req_sync.io.deq_reset := reset
dtm_req := req_sync.io.deq
jtag_dtm.io.dtm_resp := resp_sync.io.deq
resp_sync.io.deq_clock.get := io.jtag.TCK
resp_sync.io.deq_reset.get := io.jtag.TRST
resp_sync.io.enq_clock.get := clock
resp_sync.io.enq_reset.get := reset
resp_sync.io.enq := dtm_resp
jtag_dtm.io.dtm_resp := resp_sync.io.deq
resp_sync.io.deq_clock := io.jtag.TCK
resp_sync.io.deq_reset := io.jtag.TRST
resp_sync.io.enq_clock := clock
resp_sync.io.enq_reset := reset
resp_sync.io.enq := dtm_resp
}
}
@ -121,6 +121,5 @@ class AsyncMailbox extends BlackBox {
// this mailbox just has a fixed width of 64 bits, which is enough
// for our specific purpose here.
val io = new Crossing(UInt(width=64), true, true)
val io = new Crossing(UInt(width=64))
}