riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink: allow FIFO caches

Browse Source 
Probably not a smart thing to build, but not illegal!
This commit is contained in:
Wesley W. Terpstra 2018-02-15 19:09:37 -08:00
parent acecc407a5
commit ecd069dca4
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/tilelink/Parameters.scala
View File

@ -186,7 +186,7 @@ case class TLClientParameters(
name: String, name: String,
sourceId: IdRange = IdRange(0,1), sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(), nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false, // only a request, not a requirement requestFifo: Boolean = false, // only a request, not a requirement. applies to A, not C.
// Supports both Probe+Grant of these sizes // Supports both Probe+Grant of these sizes
supportsProbe: TransferSizes = TransferSizes.none, supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none,
@ -204,8 +204,6 @@ case class TLClientParameters(
require (supportsProbe.contains(supportsPutFull)) require (supportsProbe.contains(supportsPutFull))
require (supportsProbe.contains(supportsPutPartial)) require (supportsProbe.contains(supportsPutPartial))
require (supportsProbe.contains(supportsHint)) require (supportsProbe.contains(supportsHint))
// If you need FIFO, you better not be TL-C (due to independent A vs. C order)
require (!requestFifo || !supportsProbe)
val maxTransfer = List( val maxTransfer = List(
supportsProbe.max, supportsProbe.max,