riscv/rocket-chip
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Replace nbcache manipulation of meta state bits with abstracted functions

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This commit is contained in:
Henry Cook 2012-02-15 13:54:36 -08:00
parent 76cacbd991
commit ecbf47fe16
1 changed files with 1 additions and 1 deletions
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uncore/coherence.scala
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@ -76,7 +76,7 @@ trait ThreeStateIncoherence {
def newStateOnFlush() = tileInvalid def newStateOnFlush() = tileInvalid
def newState(cmd: Bits, state: UFix): UFix = { def newState(cmd: Bits, state: UFix): UFix = {
val (read, write) = cpuCmdToRW(cmd) val (read, write) = cpuCmdToRW(cmd)
Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), tileInvalid)) Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
} }
def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state) def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
def newStateOnPrimaryMiss(cmd: Bits): UFix = newState(cmd, tileInvalid) def newStateOnPrimaryMiss(cmd: Bits): UFix = newState(cmd, tileInvalid)