riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Replace nbcache manipulation of meta state bits with abstracted functions

Browse Source
This commit is contained in:
Henry Cook 2012-02-15 13:54:36 -08:00
parent 76cacbd991
commit ecbf47fe16
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
uncore/coherence.scala
View File

@ -76,7 +76,7 @@ trait ThreeStateIncoherence {
def newStateOnFlush() = tileInvalid
def newState(cmd: Bits, state: UFix): UFix = {
val (read, write) = cpuCmdToRW(cmd)
Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), tileInvalid))
Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
}
def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
def newStateOnPrimaryMiss(cmd: Bits): UFix = newState(cmd, tileInvalid)