riscv/rocket-chip
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make sure trackers can handle case where there are no caching clients

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This commit is contained in:
Howard Mao 2016-06-27 16:29:51 -07:00
parent a93a70c8ec
commit ec5b9dfc86
1 changed files with 27 additions and 15 deletions
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18
uncore/src/main/scala/trackers.scala
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@ -3,6 +3,7 @@
package uncore package uncore
import Chisel._ import Chisel._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import scala.math.max
class TrackerAllocation extends Bundle { class TrackerAllocation extends Bundle {
val matches = Bool(OUTPUT) val matches = Bool(OUTPUT)
@ -321,17 +322,25 @@ trait EmitsInnerProbes extends HasBlockAddressBuffer
with HasPendingBitHelpers { with HasPendingBitHelpers {
def io: HierarchicalXactTrackerIO def io: HierarchicalXactTrackerIO
val pending_iprbs = Reg(UInt(width = innerNCachingClients)) val needs_probes = (innerNCachingClients > 0)
val pending_iprbs = Reg(UInt(width = max(innerNCachingClients, 1)))
val curr_probe_dst = PriorityEncoder(pending_iprbs) val curr_probe_dst = PriorityEncoder(pending_iprbs)
val irel_counter = Wire(new TwoWayBeatCounterStatus)
def full_representation: UInt def full_representation: UInt
def initializeProbes() { pending_iprbs := full_representation & ~io.incoherent.toBits } def initializeProbes() {
if (needs_probes)
pending_iprbs := full_representation & ~io.incoherent.toBits
else
pending_iprbs := UInt(0)
}
def irel_same_xact = io.irel().conflicts(xact_addr_block) && def irel_same_xact = io.irel().conflicts(xact_addr_block) &&
!io.irel().isVoluntary() && !io.irel().isVoluntary() &&
state === s_inner_probe state === s_inner_probe
def innerProbe(prb: Probe, next: UInt) { def innerProbe(prb: Probe, next: UInt) {
if (needs_probes) {
val irel_counter = Wire(new TwoWayBeatCounterStatus)
pending_iprbs := pending_iprbs & dropPendingBitAtDest(io.inner.probe) pending_iprbs := pending_iprbs & dropPendingBitAtDest(io.inner.probe)
io.inner.probe.valid := state === s_inner_probe && pending_iprbs.orR io.inner.probe.valid := state === s_inner_probe && pending_iprbs.orR
io.inner.probe.bits := prb io.inner.probe.bits := prb
@ -346,6 +355,9 @@ trait EmitsInnerProbes extends HasBlockAddressBuffer
when(state === s_inner_probe && !(pending_iprbs.orR || irel_counter.pending)) { when(state === s_inner_probe && !(pending_iprbs.orR || irel_counter.pending)) {
state := next state := next
} }
} else {
when (state === s_inner_probe) { state := next }
}
//N.B. no pending bits added to scoreboard because all handled in s_inner_probe //N.B. no pending bits added to scoreboard because all handled in s_inner_probe
} }