riscv/rocket-chip
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Support M-mode-only implementations

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This commit is contained in:
Andrew Waterman 2016-05-25 15:40:53 -07:00
parent da105a5944
commit ec0d178010
4 changed files with 5 additions and 3 deletions
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2
riscv-tools

@ -1 +1 @@
Subproject commit ffd20b64afa18acdc60bc799346477d96236f21d Subproject commit 5e9763fe7306e1214fc6babf05b3f15728932738

2
rocket

@ -1 +1 @@
Subproject commit 8df0593d0ed0c2e58f3687c37ac03784fcad075f Subproject commit 05b951ba6f9cce36b0a3b29af9be7bd643ba2b66

2
src/main/scala/Configs.scala
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@ -204,6 +204,7 @@ class BaseConfig extends Config (
case FetchWidth => 1 case FetchWidth => 1
case RetireWidth => 1 case RetireWidth => 1
case UseVM => true case UseVM => true
case UseUser => true
case UsePerfCounters => true case UsePerfCounters => true
case FastLoadWord => true case FastLoadWord => true
case FastLoadByte => false case FastLoadByte => false
@ -392,6 +393,7 @@ class WithRV32 extends Config(
(pname,site,here) => pname match { (pname,site,here) => pname match {
case XLen => 32 case XLen => 32
case UseVM => false case UseVM => false
case UseUser => false
case UseAtomics => false case UseAtomics => false
case UseFPU => false case UseFPU => false
case _ => throw new CDEMatchError case _ => throw new CDEMatchError

2
uncore

@ -1 +1 @@
Subproject commit 2b1da9213aa43cb37d3e7da7d9146825856ec6ef Subproject commit 1bb32abf97b256be31f8876579e27c2fd9f5a958