riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Increase tag width for configurable precision in Hwacha

Browse Source
This commit is contained in:
Quan Nguyen 2013-12-13 03:33:02 -08:00
parent d450b85483
commit ebec444ad2
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/tile.scala
View File

@ -12,7 +12,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
fastLoadByte: Boolean = false, fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true) fastMulDiv: Boolean = true)
{ {
val dcacheReqTagBits = 9 // enforce compliance with require() val dcacheReqTagBits = 10 // enforce compliance with require() // hue hue hue
val xprlen = 64 val xprlen = 64
val nxpr = 32 val nxpr = 32
val nxprbits = log2Up(nxpr) val nxprbits = log2Up(nxpr)