riscv/rocket-chip
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LFSR: use random intial value of the start register

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We just need to make sure it doesn't initialize randomly stuck at 0.
This commit is contained in:
Wesley W. Terpstra 2017-03-13 13:16:17 -07:00
parent d2da33e4b1
commit eaf474a081
1 changed files with 4 additions and 3 deletions
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7
src/main/scala/uncore/tilelink2/Fuzzer.scala
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@ -37,10 +37,11 @@ object LFSR64
def apply(increment: Bool = Bool(true)): UInt =
{
val wide = 64
val undef = Reg(UInt(width = wide)) // random value based on simulation seed
val lfsr = RegInit(Mux(undef === UInt(0), UInt(1), undef))
val lfsr = Reg(UInt(width = wide)) // random initial value based on simulation seed
val xor = lfsr(0) ^ lfsr(1) ^ lfsr(3) ^ lfsr(4)
when (increment) { lfsr := Cat(xor, lfsr(wide-1,1)) }
when (increment) {
lfsr := Mux(lfsr === UInt(0), UInt(1), Cat(xor, lfsr(wide-1,1)))
}
lfsr
}
}