riscv/rocket-chip
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refactor I$ config; remove Top class

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This commit is contained in:
Andrew Waterman
2012-11-04 16:59:36 -08:00
parent 7380c9fe60
commit e9eca6a95d
3 changed files with 10 additions and 106 deletions
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7
rocket/src/main/scala/tile.scala
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@ -5,6 +5,9 @@ import Node._
import Constants._
import uncore._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
icache: ICacheConfig)
class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends Component(resetSignal)
{
val io = new Bundle {
@ -13,7 +16,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
}
val cpu = new rocketProc
val icache = new Frontend(ICacheConfig(4, 1)) // 128 sets x 4 ways (32KB)
val icache = new Frontend(conf.icache)
val dcache = new HellaCache
val arbiter = new rocketMemArbiter(DMEM_PORTS)
@ -31,7 +34,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
if (HAVE_VEC)
{
val vicache = new Frontend(ICacheConfig(128, 1)) // 128 sets x 1 ways (8KB)
val vicache = new Frontend(ICacheConfig(128, 1, conf.co)) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(DMEM_VICACHE) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}