riscv/rocket-chip
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refactor I$ config; remove Top class

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This commit is contained in:
Andrew Waterman
2012-11-04 16:59:36 -08:00
parent 7380c9fe60
commit e9eca6a95d
3 changed files with 10 additions and 106 deletions
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9
rocket/src/main/scala/icache.scala
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@ -6,7 +6,8 @@ import Constants._
import uncore._
import Util._
case class ICacheConfig(sets: Int, assoc: Int, parity: Boolean = false)
case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
parity: Boolean = false)
{
val w = 1
val ibytes = INST_BITS/8
@ -50,7 +51,7 @@ class IOCPUFrontend extends Bundle {
val ptw = new IOTLBPTW().flip
}
class Frontend(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Component
class Frontend(c: ICacheConfig) extends Component
{
val io = new Bundle {
val cpu = new IOCPUFrontend().flip
@ -122,7 +123,7 @@ class Frontend(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Comp
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
}
class ICache(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Component
class ICache(c: ICacheConfig) extends Component
{
val io = new Bundle {
val req = new PipeIO()(new Bundle {
@ -246,7 +247,7 @@ class ICache(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Compon
// output signals
io.resp.valid := s2_hit
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits := conf.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.xact_init.bits := c.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.xact_finish <> finish_q.io.deq
// control state machine