riscv/rocket-chip
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pipeline host pcr access

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This commit is contained in:
Andrew Waterman
2012-12-06 14:22:07 -08:00
parent 4dda38204f
commit e9752f1d72
1 changed files with 22 additions and 8 deletions
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30
rocket/src/main/scala/dpath_util.scala
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@@ -153,14 +153,28 @@ class PCR(implicit conf: RocketConfiguration) extends Component
val rdata = Bits(); val rdata = Bits();
val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr(4,0)) val host_pcr_req_valid = Reg{Bool()} // don't reset
io.host.pcr_rep.valid := io.host.pcr_req.fire() val host_pcr_req_fire = host_pcr_req_valid && !io.r.en && !io.w.en
io.host.pcr_rep.bits := rdata val host_pcr_rep_valid = Reg{Bool()} // don't reset
val host_pcr_bits = Reg{io.host.pcr_req.bits.clone}
io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
io.host.pcr_rep.valid := host_pcr_rep_valid
io.host.pcr_rep.bits := host_pcr_bits.data
when (io.host.pcr_req.fire()) {
host_pcr_req_valid := true
host_pcr_bits := io.host.pcr_req.bits
}
when (host_pcr_req_fire) {
host_pcr_req_valid := false
host_pcr_rep_valid := true
host_pcr_bits.data := rdata
}
when (io.host.pcr_rep.fire()) { host_pcr_rep_valid := false }
val wen = io.w.en || !io.r.en && io.host.pcr_req.valid && io.host.pcr_req.bits.rw val raddr = Mux(io.r.en, io.r.addr, host_pcr_bits.addr)
val waddr = Mux(io.w.en, io.w.addr, io.host.pcr_req.bits.addr) val wen = io.w.en || !io.r.en && host_pcr_req_valid && host_pcr_bits.rw
val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data) val waddr = Mux(io.w.en, io.w.addr, host_pcr_bits.addr)
io.host.pcr_req.ready := !io.w.en && !io.r.en val wdata = Mux(io.w.en, io.w.data, host_pcr_bits.data)
io.status := reg_status io.status := reg_status
io.ptbr_wen := wen && waddr === PTBR io.ptbr_wen := wen && waddr === PTBR
@@ -210,7 +224,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
io.host.ipi_req.bits := io.w.data io.host.ipi_req.bits := io.w.data
io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === TOHOST) { reg_tohost := UFix(0) } when (host_pcr_req_fire && !host_pcr_bits.rw && host_pcr_bits.addr === TOHOST) { reg_tohost := UFix(0) }
val read_impl = Bits(2) val read_impl = Bits(2)
val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS