riscv/rocket-chip
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rocketchip: all of the address map now comes from TL2

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 18:29:16 -07:00
parent 401fd378b4
commit e9725aea2f
6 changed files with 14 additions and 33 deletions
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8
src/main/scala/rocketchip/BaseTop.scala
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@@ -31,16 +31,18 @@ abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(impli
// Add a SoC and peripheral bus
val socBus = LazyModule(new TLXbar)
val peripheryBus = LazyModule(new TLXbar)
lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
// Fill in the TL1 legacy parameters
implicit val p = q.alterPartial {
case NCoreplexExtClients => pBusMasters.sum
case NExtInterrupts => pInterrupts.sum
case GlobalAddrMap => GenerateGlobalAddrMap(q, peripheryManagers)
case GlobalAddrMap => legacyAddrMap
}
val coreplex = LazyModule(buildCoreplex(p))
val coreplex : C = LazyModule(buildCoreplex(p))
// Create the address map for legacy masters
lazy val legacyAddrMap = GenerateGlobalAddrMap(q, coreplex.l1tol2.node.edgesIn(0).manager.managers)
peripheryBus.node :=
TLBuffer()(