diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index e981774a..64ff77eb 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -119,7 +119,7 @@ class WithComparator extends Config( case BuildGroundTest => (p: Parameters) => Module(new ComparatorCore()(p)) case ComparatorKey => ComparatorParameters( - targets = Seq("mem", "io:TL2:testram").map(name => + targets = Seq("mem", "TL2:testram").map(name => site(GlobalAddrMap)(name).start.longValue), width = 8, operations = 1000, diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala index 093855fe..3db5ad74 100644 --- a/src/main/scala/groundtest/Regression.scala +++ b/src/main/scala/groundtest/Regression.scala @@ -71,7 +71,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()( io.mem.grant.ready := Bool(true) io.cache.req.valid := !get_sent && started - io.cache.req.bits.addr := UInt(addrMap("io:TL2:bootrom").start) + io.cache.req.bits.addr := UInt(addrMap("TL2:bootrom").start) io.cache.req.bits.typ := MT_WU io.cache.req.bits.cmd := M_XRD io.cache.req.bits.tag := UInt(0) diff --git a/src/main/scala/junctions/addrmap.scala b/src/main/scala/junctions/addrmap.scala index 56158001..86fdd276 100644 --- a/src/main/scala/junctions/addrmap.scala +++ b/src/main/scala/junctions/addrmap.scala @@ -76,12 +76,7 @@ class AddrMap( var cacheable = true for (AddrMapEntry(name, r) <- entriesIn) { require (!mapping.contains(name)) - - if (r.start != 0) { - base = r.start - } else { - base = (base + r.size - 1) / r.size * r.size - } + base = r.start r match { case r: AddrMap => diff --git a/src/main/scala/rocket/dcache.scala b/src/main/scala/rocket/dcache.scala index e0294bca..4fccc725 100644 --- a/src/main/scala/rocket/dcache.scala +++ b/src/main/scala/rocket/dcache.scala @@ -127,7 +127,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { require(nWays == 1) metaWriteArb.io.out.ready := true metaReadArb.io.out.ready := !metaWriteArb.io.out.valid - val inScratchpad = addrMap(s"io:cbus:dmem${tileId}").containsAddress(s1_paddr) + val inScratchpad = addrMap(s"TL2:dmem${tileId}").containsAddress(s1_paddr) val hitState = Mux(inScratchpad, ClientMetadata.onReset.onHit(M_XWR), ClientMetadata.onReset) (inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset)) } else { diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 6b57835c..9258b34b 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -31,16 +31,18 @@ abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(impli // Add a SoC and peripheral bus val socBus = LazyModule(new TLXbar) val peripheryBus = LazyModule(new TLXbar) - lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers // Fill in the TL1 legacy parameters implicit val p = q.alterPartial { case NCoreplexExtClients => pBusMasters.sum case NExtInterrupts => pInterrupts.sum - case GlobalAddrMap => GenerateGlobalAddrMap(q, peripheryManagers) + case GlobalAddrMap => legacyAddrMap } - val coreplex = LazyModule(buildCoreplex(p)) + val coreplex : C = LazyModule(buildCoreplex(p)) + + // Create the address map for legacy masters + lazy val legacyAddrMap = GenerateGlobalAddrMap(q, coreplex.l1tol2.node.edgesIn(0).manager.managers) peripheryBus.node := TLBuffer()( diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala index 33c59533..f44cc105 100644 --- a/src/main/scala/rocketchip/Utils.scala +++ b/src/main/scala/rocketchip/Utils.scala @@ -54,19 +54,7 @@ class GlobalVariable[T] { object GenerateGlobalAddrMap { def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = { - lazy val cBusIOAddrMap: AddrMap = { - val entries = collection.mutable.ArrayBuffer[AddrMapEntry]() - entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX))) - entries += AddrMapEntry("plic", MemRange(0x0C000000, 0x4000000, MemAttr(AddrMapProt.RW))) - if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles - require(p(NTiles) == 1) // TODO relax this - require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM - entries += AddrMapEntry("dmem0", MemRange(0x80000000L, BigInt(p(DataScratchpadSize)), MemAttr(AddrMapProt.RWX))) - } - new AddrMap(entries) - } - - lazy val tl2Devices = peripheryManagers.map { manager => + val tl2Devices = peripheryManagers.map { manager => val cacheable = manager.regionType match { case RegionType.CACHED => true case RegionType.TRACKED => true @@ -84,22 +72,18 @@ object GenerateGlobalAddrMap { } }.flatten - lazy val uniquelyNamedTL2Devices = + val uniquelyNamedTL2Devices = tl2Devices.groupBy(_.name).values.map(_.zipWithIndex.map { case (e, i) => if (i == 0) e else e.copy(name = e.name + "_" + i) }).flatten.toList - lazy val tl2AddrMap = new AddrMap(uniquelyNamedTL2Devices, collapse = true) - val memBase = 0x80000000L val memSize = p(ExtMemSize) Dump("MEM_BASE", memBase) - val cBus = AddrMapEntry("cbus", cBusIOAddrMap) - val tlBus = AddrMapEntry("TL2", tl2AddrMap) - val io = AddrMapEntry("io", AddrMap(cBus, tlBus)) + val tl2 = AddrMapEntry("TL2", new AddrMap(uniquelyNamedTL2Devices, collapse = true)) val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))) - AddrMap((io +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*) + AddrMap((tl2 +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*) } } @@ -107,7 +91,7 @@ object GenerateConfigString { def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = { val c = CoreplexParameters()(p) val addrMap = p(GlobalAddrMap) - val plicAddr = addrMap("io:cbus:plic").start + val plicAddr = addrMap("TL2:plic").start val clint = CoreplexLocalInterrupterConfig() val xLen = p(XLen) val res = new StringBuilder