riscv/rocket-chip
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rocketchip: all of the address map now comes from TL2

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Wesley W. Terpstra committed 2016-10-31 11:42:44 -07:00
1 parent 401fd378b4
commit e9725aea2f
6 files changed
+14 -33
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src/main/scala/rocket/dcache.scala
+1 -1
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@@ -127,7 +127,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
require(nWays == 1)
metaWriteArb.io.out.ready := true
metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
val inScratchpad = addrMap(s"io:cbus:dmem${tileId}").containsAddress(s1_paddr)
val inScratchpad = addrMap(s"TL2:dmem${tileId}").containsAddress(s1_paddr)
val hitState = Mux(inScratchpad, ClientMetadata.onReset.onHit(M_XWR), ClientMetadata.onReset)
(inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
} else {