riscv/rocket-chip
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rocketchip: all of the address map now comes from TL2

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 18:29:16 -07:00
parent 401fd378b4
commit e9725aea2f
6 changed files with 14 additions and 33 deletions
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2
src/main/scala/groundtest/Configs.scala
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@ -119,7 +119,7 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:TL2:testram").map(name =>
targets = Seq("mem", "TL2:testram").map(name =>
site(GlobalAddrMap)(name).start.longValue),
width = 8,
operations = 1000,

2
src/main/scala/groundtest/Regression.scala
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@ -71,7 +71,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:TL2:bootrom").start)
io.cache.req.bits.addr := UInt(addrMap("TL2:bootrom").start)
io.cache.req.bits.typ := MT_WU
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)