riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Sync with riscv-opcodes (csr register mapping)

Browse Source
This commit is contained in:
Stephen Twigg 2014-04-08 15:48:37 -07:00
parent 3ed8adf032
commit e90f2484aa
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/instructions.scala
View File

@ -221,6 +221,7 @@ object CSRs {
val fflags = 0x1 val fflags = 0x1
val frm = 0x2 val frm = 0x2
val fcsr = 0x3 val fcsr = 0x3
val stats = 0xc0
val sup0 = 0x500 val sup0 = 0x500
val sup1 = 0x501 val sup1 = 0x501
val epc = 0x502 val epc = 0x502
@ -237,7 +238,6 @@ object CSRs {
val fatc = 0x50d val fatc = 0x50d
val send_ipi = 0x50e val send_ipi = 0x50e
val clear_ipi = 0x50f val clear_ipi = 0x50f
val stats = 0x51c
val reset = 0x51d val reset = 0x51d
val tohost = 0x51e val tohost = 0x51e
val fromhost = 0x51f val fromhost = 0x51f
@ -269,6 +269,7 @@ object CSRs {
res += fflags res += fflags
res += frm res += frm
res += fcsr res += fcsr
res += stats
res += sup0 res += sup0
res += sup1 res += sup1
res += epc res += epc
@ -285,7 +286,6 @@ object CSRs {
res += fatc res += fatc
res += send_ipi res += send_ipi
res += clear_ipi res += clear_ipi
res += stats
res += reset res += reset
res += tohost res += tohost
res += fromhost res += fromhost