riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

make taking max of multiple integers in config a bit easier

Browse Source
This commit is contained in:
Howard Mao 2016-03-16 14:21:47 -07:00
parent 4fc2a14a63
commit e90a9dfb2b
2 changed files with 17 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/main/scala/Configs.scala
View File

@ -13,6 +13,13 @@ import scala.math.max
import DefaultTestSuites._ import DefaultTestSuites._
import cde.{Parameters, Config, Dump, Knob} import cde.{Parameters, Config, Dump, Knob}
object ConfigUtils {
def max_int(values: Int*): Int = {
values.reduce((a, b) => max(a, b))
}
}
import ConfigUtils._
class DefaultConfig extends Config ( class DefaultConfig extends Config (
topDefinitions = { (pname,site,here) => topDefinitions = { (pname,site,here) =>
type PF = PartialFunction[Any,Any] type PF = PartialFunction[Any,Any]
@ -77,11 +84,10 @@ class DefaultConfig extends Config (
// Bits added by NASTI interconnect // Bits added by NASTI interconnect
max(log2Up(site(MaxBanksPerMemoryChannel)), max(log2Up(site(MaxBanksPerMemoryChannel)),
(if (site(UseDma)) 3 else 2))) (if (site(UseDma)) 3 else 2)))
case MIFMasterTagBits => log2Up(max( case MIFMasterTagBits => log2Up(max_int(
site(NTiles), site(NTiles),
max( site(NAcquireTransactors)+2,
site(NAcquireTransactors)+2, site(NDmaTransactors)))
site(NDmaTransactors))))
case MIFDataBits => Dump("MIF_DATA_BITS", 64) case MIFDataBits => Dump("MIF_DATA_BITS", 64)
case MIFAddrBits => Dump("MIF_ADDR_BITS", case MIFAddrBits => Dump("MIF_ADDR_BITS",
site(PAddrBits) - site(CacheBlockOffsetBits)) site(PAddrBits) - site(CacheBlockOffsetBits))
@ -195,9 +201,9 @@ class DefaultConfig extends Config (
site(NTiles) * site(NTiles) *
(1 + (if(site(BuildRoCC).isEmpty) 0 (1 + (if(site(BuildRoCC).isEmpty) 0
else site(RoccNMemChannels))), else site(RoccNMemChannels))),
maxClientXacts = max(site(NMSHRs) + 1, maxClientXacts = max_int(site(NMSHRs) + 1,
max(if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts), if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
if (site(UseDma)) 4 else 1)), if (site(UseDma)) 4 else 1),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2, maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) + 1 else 1), if (site(UseDma)) site(NDmaTransactors) + 1 else 1),
maxManagerXacts = site(NAcquireTransactors) + 2, maxManagerXacts = site(NAcquireTransactors) + 2,

7
src/main/scala/TestConfigs.scala
View File

@ -8,6 +8,7 @@ import junctions._
import scala.collection.mutable.LinkedHashSet import scala.collection.mutable.LinkedHashSet
import cde.{Parameters, Config, Dump, Knob} import cde.{Parameters, Config, Dump, Knob}
import scala.math.max import scala.math.max
import ConfigUtils._
class WithGroundTest extends Config( class WithGroundTest extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
@ -17,9 +18,9 @@ class WithGroundTest extends Config(
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1, nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NTiles), nCachingClients = site(NTiles),
nCachelessClients = site(NTiles) + (if (site(UseDma)) 2 else 1), nCachelessClients = site(NTiles) + (if (site(UseDma)) 2 else 1),
maxClientXacts = max(site(NMSHRs) + 1, maxClientXacts = max_int(site(NMSHRs) + 1,
max(site(GroundTestMaxXacts), if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
if (site(UseDma)) 4 else 1)), if (site(UseDma)) 4 else 1),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2, maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) + 1 else 1), if (site(UseDma)) site(NDmaTransactors) + 1 else 1),
maxManagerXacts = site(NAcquireTransactors) + 2, maxManagerXacts = site(NAcquireTransactors) + 2,