riscv/rocket-chip
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unit tests: do not use LFSR16 which has a common seed!

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We want each LFSR to generate independent noise.
This commit is contained in:
Wesley W. Terpstra 2017-10-30 15:01:17 -07:00
parent ec70e5fb02
commit e8ed450f13
3 changed files with 6 additions and 4 deletions
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3
src/main/scala/amba/ahb/SRAM.scala
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@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.tilelink.LFSRNoiseMaker
class AHBRAM( class AHBRAM(
address: AddressSet, address: AddressSet,
@ -92,7 +93,7 @@ class AHBRAM(
when (a_request) { d_request := Bool(true) } when (a_request) { d_request := Bool(true) }
// Finally, the outputs // Finally, the outputs
in.hreadyout := (if(fuzzHreadyout) { !d_request || LFSR16(Bool(true))(0) } else { Bool(true) }) in.hreadyout := (if(fuzzHreadyout) { !d_request || LFSRNoiseMaker(1)(0) } else { Bool(true) })
in.hresp := Mux(d_legal || !in.hreadyout, AHBParameters.RESP_OKAY, AHBParameters.RESP_ERROR) in.hresp := Mux(d_legal || !in.hreadyout, AHBParameters.RESP_OKAY, AHBParameters.RESP_ERROR)
in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0)) in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0))
} }

5
src/main/scala/amba/apb/SRAM.scala
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@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.tilelink.LFSRNoiseMaker
class APBRAM( class APBRAM(
address: AddressSet, address: AddressSet,
@ -39,8 +40,8 @@ class APBRAM(
mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools) mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools)
} }
in.pready := Bool(!fuzzReady) || LFSR16(!in.penable)(0) in.pready := Bool(!fuzzReady) || LFSRNoiseMaker(1)(0)
in.pslverr := RegEnable(!legal, !in.penable) || (Bool(fuzzError) && LFSR16(Bool(true))(0)) in.pslverr := RegEnable(!legal, !in.penable) || (Bool(fuzzError) && LFSRNoiseMaker(1)(0))
in.prdata := mem.readAndHold(paddr, read).asUInt in.prdata := mem.readAndHold(paddr, read).asUInt
} }
} }

2
src/main/scala/tilelink/Delayer.scala
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@ -14,7 +14,7 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T], noise: T) { def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T], noise: T) {
val allow = UInt((q * 65535.0).toInt) <= LFSR16(source.valid) val allow = UInt((q * 65535.0).toInt) <= LFSRNoiseMaker(16, source.valid)
sink.valid := source.valid && allow sink.valid := source.valid && allow
source.ready := sink.ready && allow source.ready := sink.ready && allow
sink.bits := source.bits sink.bits := source.bits