48 lines
1.6 KiB
Scala
48 lines
1.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.apb
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import freechips.rocketchip.tilelink.LFSRNoiseMaker
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class APBRAM(
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address: AddressSet,
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executable: Boolean = true,
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beatBytes: Int = 4,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil,
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fuzzReady: Boolean = false,
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fuzzError: Boolean = false)
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(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName)
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{
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val node = APBSlaveNode(Seq(APBSlavePortParameters(
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Seq(APBSlaveParameters(
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address = List(address) ++ errors,
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resources = resources,
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regionType = RegionType.UNCACHED,
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executable = executable,
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supportsRead = true,
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supportsWrite = true)),
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beatBytes = beatBytes)))
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lazy val module = new LazyModuleImp(this) {
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val (in, _) = node.in(0)
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val mem = makeSinglePortedByteWriteSeqMem(1 << mask.filter(b=>b).size)
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val paddr = Cat((mask zip (in.paddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
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val legal = address.contains(in.paddr)
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val read = in.psel && !in.penable && !in.pwrite
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when (in.psel && !in.penable && in.pwrite && legal) {
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mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools)
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}
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in.pready := Bool(!fuzzReady) || LFSRNoiseMaker(1)(0)
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in.pslverr := RegEnable(!legal, !in.penable) || (Bool(fuzzError) && LFSRNoiseMaker(1)(0))
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in.prdata := mem.readAndHold(paddr, read).asUInt
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}
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}
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