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unit tests: do not use LFSR16 which has a common seed!

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We want each LFSR to generate independent noise.
This commit is contained in:
Wesley W. Terpstra
2017-10-30 15:01:17 -07:00
parent ec70e5fb02
commit e8ed450f13
3 changed files with 6 additions and 4 deletions
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5
src/main/scala/amba/apb/SRAM.scala
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@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink.LFSRNoiseMaker
class APBRAM(
address: AddressSet,
@ -39,8 +40,8 @@ class APBRAM(
mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools)
}
in.pready := Bool(!fuzzReady) || LFSR16(!in.penable)(0)
in.pslverr := RegEnable(!legal, !in.penable) || (Bool(fuzzError) && LFSR16(Bool(true))(0))
in.pready := Bool(!fuzzReady) || LFSRNoiseMaker(1)(0)
in.pslverr := RegEnable(!legal, !in.penable) || (Bool(fuzzError) && LFSRNoiseMaker(1)(0))
in.prdata := mem.readAndHold(paddr, read).asUInt
}
}