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plic: Use same recoding technique on complete as well as claim

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This commit is contained in:
Megan Wachs 2017-06-30 08:36:00 -07:00
parent 3dca2bc4a3
commit e8e709c941
1 changed files with 23 additions and 9 deletions
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30
src/main/scala/uncore/devices/Plic.scala
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@ -176,18 +176,33 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
}
// When a hart reads its claim/complete register, then the
// device which is currently its highest priority is no longer pending.
// This code expolits the fact that only one hart can claim a device at
// a time through the TL interface.
// Note: PLIC doesn't care which hart reads the register.
val claimer = Wire(Vec(nHarts, Bool()))
val claiming = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i), nDevices+1), UInt(0))}
val claimedDevs = Vec(claiming.reduceLeft( _ | _ ).toBools)
((pending zip gateways) zip claimedDevs) foreach { case ((p, g), c) =>
g.ready := !p
g.complete := false
when(c) {
p := false
}.elsewhen (g.valid) {
p := true
when (c || g.valid) { p := !c }
}
// When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that
// hart) is marked complete.
// This code expolits the fact that only one hart can complete a device at
// a time through the TL interface
// (Note -- PLIC doesn't care which hart writes the register)
val completer = Wire(Vec(nHarts, Bool()))
val completingDevs = Wire(Vec(nHarts, UInt(width = log2Up(pending.size))))
val completing = Vec.tabulate(nHarts){i => Mux(completer(i), UIntToOH(completingDevs(i), nDevices+1), UInt(0))}
val completedDevs = Vec(completing.reduceLeft( _ | _ ).toBools)
(gateways zip completedDevs) foreach { case (g, c) =>
g.complete := c
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
@ -200,9 +215,8 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
},
RegWriteFn { (valid, data) =>
val irq = data.extract(log2Ceil(nDevices+1)-1, 0)
when (valid && enables(i)(irq)) {
gateways(irq).complete := Bool(true)
}
completingDevs(i) := irq
completer(i) := valid && enables(i)(irq)
Bool(true)
}
)