diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala
index 25009e60..2f73bdaa 100644
--- a/src/main/scala/uncore/devices/Plic.scala
+++ b/src/main/scala/uncore/devices/Plic.scala
@@ -176,18 +176,33 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
       PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
     }
 
+    // When a hart reads its claim/complete register, then the
+    // device which is currently its highest priority is no longer pending.
+    // This code expolits the fact that only one hart can claim a device at
+    // a time through the TL interface.
+    // Note: PLIC doesn't care which hart reads the register.
     val claimer = Wire(Vec(nHarts, Bool()))
     val claiming = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i), nDevices+1), UInt(0))}
     val claimedDevs = Vec(claiming.reduceLeft( _ | _ ).toBools)
 
     ((pending zip gateways) zip claimedDevs) foreach { case ((p, g), c) =>
       g.ready := !p
-      g.complete := false
-      when(c) {
-        p := false
-      }.elsewhen (g.valid) {
-        p := true
-      }
+      when (c || g.valid) { p := !c }
+    }
+
+    // When a hart writes a claim/complete register, then
+    // the written device (as long as it is actually enabled for that
+    // hart) is marked complete.
+    // This code expolits the fact that only one hart can complete a device at
+    // a time through the TL interface
+    // (Note -- PLIC doesn't care which hart writes the register)
+    val completer = Wire(Vec(nHarts, Bool()))
+    val completingDevs = Wire(Vec(nHarts, UInt(width = log2Up(pending.size))))
+    val completing = Vec.tabulate(nHarts){i => Mux(completer(i), UIntToOH(completingDevs(i), nDevices+1), UInt(0))}
+    val completedDevs = Vec(completing.reduceLeft( _ | _ ).toBools)
+
+    (gateways zip completedDevs) foreach { case (g, c) =>
+      g.complete := c
     }
 
     val hartRegFields = Seq.tabulate(nHarts) { i =>
@@ -200,9 +215,8 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
           },
           RegWriteFn { (valid, data) =>
             val irq = data.extract(log2Ceil(nDevices+1)-1, 0)
-            when (valid && enables(i)(irq)) {
-              gateways(irq).complete := Bool(true)
-            }
+            completingDevs(i) := irq
+            completer(i) := valid && enables(i)(irq)
             Bool(true)
           }
         )