riscv/rocket-chip
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rocketchip: traits for adding external TL2 ports

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Wesley W. Terpstra committed 2016-11-23 20:44:42 -08:00
1 parent 4b9dc78951
commit e87f54d4f7
2 files changed
+79 -10
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src/main/scala/rocketchip/Configs.scala
+3 -2
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@@ -28,8 +28,9 @@ class BasePlatformConfig extends Config(
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false
case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case _ => throw new CDEMatchError
})