riscv/rocket-chip
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New privileged ISA implementation

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This commit is contained in:
Andrew Waterman
2015-03-14 02:49:07 -07:00
parent ebbd14254c
commit e85c54cc4b
10 changed files with 690 additions and 482 deletions
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60
rocket/src/main/scala/tlb.scala
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@ -3,6 +3,7 @@
package rocket
import Chisel._
import Util._
import uncore._
import scala.math._
@ -19,7 +20,7 @@ abstract class TLBModule extends Module with TLBParameters
class CAMIO extends TLBBundle {
val clear = Bool(INPUT)
val clear_hit = Bool(INPUT)
val clear_mask = Bits(INPUT, entries)
val tag = Bits(INPUT, camTagBits)
val hit = Bool(OUTPUT)
val hits = UInt(OUTPUT, entries)
@ -40,10 +41,7 @@ class RocketCAM extends TLBModule {
cam_tags(io.write_addr) := io.write_tag
}
when (io.clear) {
vb_array := Bits(0, entries)
}
.elsewhen (io.clear_hit) {
vb_array := vb_array & ~io.hits
vb_array := vb_array & ~io.clear_mask
}
val hits = (0 until entries).map(i => vb_array(i) && cam_tags(i) === io.tag)
@ -81,6 +79,7 @@ class TLBReq extends CoreBundle {
val vpn = UInt(width = vpnBits+1)
val passthrough = Bool()
val instruction = Bool()
val store = Bool()
}
class TLBRespNoHitIndex extends CoreBundle {
@ -107,36 +106,38 @@ class TLB extends TLBModule {
val state = Reg(init=s_ready)
val r_refill_tag = Reg(UInt())
val r_refill_waddr = Reg(UInt())
val r_req = Reg(new TLBReq)
val tag_cam = Module(new RocketCAM)
val tag_ram = Mem(io.ptw.resp.bits.ppn.clone, entries)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
tag_cam.io.clear := io.ptw.invalidate
tag_cam.io.clear_hit := io.req.fire() && Mux(io.req.bits.instruction, io.resp.xcpt_if, io.resp.xcpt_ld && io.resp.xcpt_st)
tag_cam.io.tag := lookup_tag
tag_cam.io.write := state === s_wait && io.ptw.resp.valid
tag_cam.io.write_tag := r_refill_tag
tag_cam.io.write_addr := r_refill_waddr
val tag_hit = tag_cam.io.hit
val tag_hit_addr = OHToUInt(tag_cam.io.hits)
// permission bit arrays
val valid_array = Reg(Bits()) // V bit of PTE (not equivalent to CAM tag valid bit!)
val ur_array = Reg(Bits()) // user read permission
val uw_array = Reg(Bits()) // user write permission
val ux_array = Reg(Bits()) // user execute permission
val sr_array = Reg(Bits()) // supervisor read permission
val sw_array = Reg(Bits()) // supervisor write permission
val sx_array = Reg(Bits()) // supervisor execute permission
val dirty_array = Reg(Bits()) // PTE dirty bit
when (io.ptw.resp.valid) {
val perm = io.ptw.resp.bits.perm & ~io.ptw.resp.bits.error.toSInt
tag_ram(r_refill_waddr) := io.ptw.resp.bits.ppn
val perm = (!io.ptw.resp.bits.error).toSInt & io.ptw.resp.bits.perm
ur_array := ur_array.bitSet(r_refill_waddr, perm(0))
valid_array := valid_array.bitSet(r_refill_waddr, !io.ptw.resp.bits.error)
ur_array := ur_array.bitSet(r_refill_waddr, perm(0) || perm(2))
uw_array := uw_array.bitSet(r_refill_waddr, perm(1))
ux_array := ux_array.bitSet(r_refill_waddr, perm(2))
sr_array := sr_array.bitSet(r_refill_waddr, perm(3))
sr_array := sr_array.bitSet(r_refill_waddr, perm(3) || perm(5))
sw_array := sw_array.bitSet(r_refill_waddr, perm(4))
sx_array := sx_array.bitSet(r_refill_waddr, perm(5))
dirty_array := dirty_array.bitSet(r_refill_waddr, io.ptw.resp.bits.dirty)
}
// high if there are any unused (invalid) entries in the TLB
@ -144,30 +145,51 @@ class TLB extends TLBModule {
val invalid_entry = PriorityEncoder(~tag_cam.io.valid_bits)
val plru = new PseudoLRU(entries)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace)
val priv = Mux(io.ptw.status.prv === PRV_M && !io.req.bits.instruction, io.ptw.status.mprv, io.ptw.status.prv)
val priv_s = priv === PRV_S
val priv_uses_vm = priv <= PRV_S
val req_xwr = Cat(!r_req.store, r_req.store, !(r_req.instruction || r_req.store))
val req_perm = Cat(req_xwr & priv_s.toSInt, req_xwr & ~priv_s.toSInt)
val r_array = Mux(priv_s, sr_array, ur_array)
val w_array = Mux(priv_s, sw_array, uw_array)
val x_array = Mux(priv_s, sx_array, ux_array)
val vm_enabled = io.ptw.status.vm(2) && priv_uses_vm
val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1)
val tlb_hit = io.ptw.status.vm && tag_hit
val tlb_miss = io.ptw.status.vm && !tag_hit && !bad_va
// it's only a store hit if the dirty bit is set
val tag_hits = tag_cam.io.hits & (dirty_array | ~(io.req.bits.store.toSInt & w_array))
val tag_hit = tag_hits.orR
val tlb_hit = vm_enabled && tag_hit
val tlb_miss = vm_enabled && !tag_hit && !bad_va
when (io.req.valid && tlb_hit) {
plru.access(OHToUInt(tag_cam.io.hits))
}
io.req.ready := state === s_ready
io.resp.xcpt_ld := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sr_array & tag_cam.io.hits).orR, (ur_array & tag_cam.io.hits).orR)
io.resp.xcpt_st := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sw_array & tag_cam.io.hits).orR, (uw_array & tag_cam.io.hits).orR)
io.resp.xcpt_if := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sx_array & tag_cam.io.hits).orR, (ux_array & tag_cam.io.hits).orR)
io.resp.xcpt_ld := bad_va || tlb_hit && !(r_array & tag_cam.io.hits).orR
io.resp.xcpt_st := bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
io.resp.xcpt_if := bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
io.resp.miss := tlb_miss
io.resp.ppn := Mux(io.ptw.status.vm && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(params(PPNBits)-1,0))
io.resp.ppn := Mux(vm_enabled && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(params(PPNBits)-1,0))
io.resp.hit_idx := tag_cam.io.hits
// clear invalid entries on access, or all entries on a TLB flush
tag_cam.io.clear := io.ptw.invalidate || io.req.fire()
tag_cam.io.clear_mask := ~valid_array | (tag_cam.io.hits & ~tag_hits)
when (io.ptw.invalidate) { tag_cam.io.clear_mask := SInt(-1) }
io.ptw.req.valid := state === s_request
io.ptw.req.bits := r_refill_tag
io.ptw.req.bits.addr := r_refill_tag
io.ptw.req.bits.perm := req_perm
when (io.req.fire() && tlb_miss) {
state := s_request
r_refill_tag := lookup_tag
r_refill_waddr := repl_waddr
r_req := io.req.bits
}
when (state === s_request) {
when (io.ptw.invalidate) {