riscv/rocket-chip
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fix AMO replay bug

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This commit is contained in:
Andrew Waterman 2012-01-23 15:35:53 -08:00
parent d59bddfbf1
commit e7bf07d55e
1 changed files with 6 additions and 3 deletions
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9
rocket/src/main/scala/nbdcache.scala
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@ -688,6 +688,9 @@ class HellaCacheDM(lines: Int) extends Component {
val replay_amo_val = replayer.io.data_req.valid && replayer.io.data_req.bits.cmd(3).toBool val replay_amo_val = replayer.io.data_req.valid && replayer.io.data_req.bits.cmd(3).toBool
when (replay_amo_val) { when (replay_amo_val) {
r_cpu_req_idx <== Cat(replayer.io.data_req.bits.idx, replayer.io.data_req.bits.offset)
r_cpu_req_cmd <== replayer.io.data_req.bits.cmd
r_cpu_req_type <== replayer.io.data_req.bits.typ
r_cpu_req_data <== replayer.io.data_req.bits.data r_cpu_req_data <== replayer.io.data_req.bits.data
} }
when (io.cpu.req_val) { when (io.cpu.req_val) {
@ -803,9 +806,9 @@ class HellaCacheDM(lines: Int) extends Component {
p_store_data <== amoalu.io.out p_store_data <== amoalu.io.out
} }
when (tag_hit && r_req_write && p_store_rdy || r_replay_amo) { when (tag_hit && r_req_write && p_store_rdy || r_replay_amo) {
p_store_idx <== Mux(r_replay_amo, Reg(Cat(replayer.io.data_req.bits.idx, replayer.io.data_req.bits.offset)), r_cpu_req_idx) p_store_idx <== r_cpu_req_idx
p_store_type <== Mux(r_replay_amo, Reg(replayer.io.data_req.bits.typ), r_cpu_req_type) p_store_type <== r_cpu_req_type
p_store_cmd <== Mux(r_replay_amo, Reg(replayer.io.data_req.bits.cmd), r_cpu_req_cmd) p_store_cmd <== r_cpu_req_cmd
p_store_data <== storegen.io.dout p_store_data <== storegen.io.dout
} }