riscv/rocket-chip
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diplomacy: support multiple ports behind a BlindNode

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This commit is contained in:
Wesley W. Terpstra
2017-01-19 14:25:34 -08:00
parent 258abc5629
commit e7b35b4bb6
8 changed files with 43 additions and 39 deletions
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src/main/scala/rocketchip/TestHarness.scala
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@ -46,7 +46,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
val config = p(ExtMem)
val node = AXI4BlindInputNode(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits)))))
val node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits))))))
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))