diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala
index c01febf7..96e1a34b 100644
--- a/src/main/scala/diplomacy/Nodes.scala
+++ b/src/main/scala/diplomacy/Nodes.scala
@@ -224,30 +224,34 @@ class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: P
   override lazy val bundleOut = { require(false, s"${name} has no bundleOut; try bundleIn?"); bundleIn }
 }
 
-class BlindOutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI)
-  extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, 1 to 1)
+class BlindOutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: Seq[PI])
+  extends SimpleNode(imp)({case (0, _) => Seq()}, {case (_, Seq()) => pi}, 0 to 0, pi.size to pi.size)
 {
+  require (!pi.isEmpty)
   override val flip = true
   override lazy val bundleOut = bundleIn
 }
 
-class BlindInputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO)
-  extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, 1 to 1, 0 to 0)
+class BlindInputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: Seq[PO])
+  extends SimpleNode(imp)({case (_, Seq()) => po}, {case (0, _) => Seq()}, po.size to po.size, 0 to 0)
 {
+  require (!po.isEmpty)
   override val flip = true
   override lazy val bundleIn = bundleOut
 }
 
-class InternalOutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI)
-  extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, 1 to 1)
+class InternalOutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: Seq[PI])
+  extends SimpleNode(imp)({case (0, _) => Seq()}, {case (_, Seq()) => pi}, 0 to 0, pi.size to pi.size)
 {
+  require (!pi.isEmpty)
   override val wire = true
   override lazy val bundleOut = bundleIn
 }
 
-class InternalInputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO)
-  extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, 1 to 1, 0 to 0)
+class InternalInputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: Seq[PO])
+  extends SimpleNode(imp)({case (_, Seq()) => po}, {case (0, _) => Seq()}, po.size to po.size, 0 to 0)
 {
+  require (!po.isEmpty)
   override val wire = true
   override lazy val bundleIn = bundleOut
 }
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 64e95e6b..bede976d 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -91,7 +91,7 @@ trait PeripheryMasterAXI4Mem {
     val c_size = config.size/channels
     val c_base = config.base + c_size*i
 
-    AXI4BlindOutputNode(AXI4SlavePortParameters(
+    AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
       slaves = Seq(AXI4SlaveParameters(
         address       = List(AddressSet(c_base, c_size-1)),
         regionType    = RegionType.UNCACHED,   // cacheable
@@ -99,7 +99,7 @@ trait PeripheryMasterAXI4Mem {
         supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
         supportsRead  = TransferSizes(1, 256),
         interleavedId = Some(0))),             // slave does not interleave read responses
-      beatBytes = config.beatBytes))
+      beatBytes = config.beatBytes)))
   }
 
   val mem = mem_axi4.map { node =>
@@ -130,14 +130,14 @@ trait PeripheryMasterAXI4MMIO {
   this: TopNetwork =>
 
   private val config = p(ExtBus)
-  val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
+  val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(BigInt(config.base), config.size-1)),
       executable    = true,                  // Can we run programs on this memory?
       supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
       supportsRead  = TransferSizes(1, 256),
       interleavedId = Some(0))),             // slave does not interleave read responses
-    beatBytes = config.beatBytes))
+    beatBytes = config.beatBytes)))
 
   mmio_axi4 :=
     AXI4Buffer()(
@@ -167,9 +167,9 @@ trait PeripheryMasterAXI4MMIOModule {
 // PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
 trait PeripherySlaveAXI4 extends L2Crossbar {
   private val config = p(ExtIn)
-  val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
+  val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
     masters = Seq(AXI4MasterParameters(
-      id = IdRange(0, 1 << config.idBits)))))
+      id = IdRange(0, 1 << config.idBits))))))
 
   l2.node :=
     TLSourceShrinker(1 << config.sourceBits)(
@@ -197,14 +197,14 @@ trait PeripheryMasterTLMMIO {
   this: TopNetwork =>
 
   private val config = p(ExtBus)
-  val mmio_tl = TLBlindOutputNode(TLManagerPortParameters(
+  val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
     managers = Seq(TLManagerParameters(
       address            = List(AddressSet(BigInt(config.base), config.size-1)),
       executable         = true,
       supportsGet        = TransferSizes(1, cacheBlockBytes),
       supportsPutFull    = TransferSizes(1, cacheBlockBytes),
       supportsPutPartial = TransferSizes(1, cacheBlockBytes))),
-    beatBytes = config.beatBytes))
+    beatBytes = config.beatBytes)))
 
   mmio_tl :=
     TLBuffer()(
@@ -233,9 +233,9 @@ trait PeripheryMasterTLMMIOModule {
 // NOTE: this port is NOT allowed to issue Acquires
 trait PeripherySlaveTL extends L2Crossbar {
   private val config = p(ExtIn)
-  val l2_tl = TLBlindInputNode(TLClientPortParameters(
+  val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters(
     clients = Seq(TLClientParameters(
-      sourceId = IdRange(0, 1 << config.idBits)))))
+      sourceId = IdRange(0, 1 << config.idBits))))))
 
   l2.node :=
     TLSourceShrinker(1 << config.sourceBits)(
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 20aaaece..35818834 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -46,7 +46,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
 class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
   val config = p(ExtMem)
 
-  val node = AXI4BlindInputNode(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits)))))
+  val node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits))))))
   val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
   sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))
 
diff --git a/src/main/scala/uncore/ahb/Nodes.scala b/src/main/scala/uncore/ahb/Nodes.scala
index 79776111..77d50c27 100644
--- a/src/main/scala/uncore/ahb/Nodes.scala
+++ b/src/main/scala/uncore/ahb/Nodes.scala
@@ -52,8 +52,8 @@ case class AHBOutputNode() extends OutputNode(AHBImp)
 case class AHBInputNode() extends InputNode(AHBImp)
 
 // Nodes used for external ports
-case class AHBBlindOutputNode(portParams: AHBSlavePortParameters) extends BlindOutputNode(AHBImp)(portParams)
-case class AHBBlindInputNode(portParams: AHBMasterPortParameters) extends BlindInputNode(AHBImp)(portParams)
+case class AHBBlindOutputNode(portParams: Seq[AHBSlavePortParameters]) extends BlindOutputNode(AHBImp)(portParams)
+case class AHBBlindInputNode(portParams: Seq[AHBMasterPortParameters]) extends BlindInputNode(AHBImp)(portParams)
 
-case class AHBInternalOutputNode(portParams: AHBSlavePortParameters) extends InternalOutputNode(AHBImp)(portParams)
-case class AHBInternalInputNode(portParams: AHBMasterPortParameters) extends InternalInputNode(AHBImp)(portParams)
+case class AHBInternalOutputNode(portParams: Seq[AHBSlavePortParameters]) extends InternalOutputNode(AHBImp)(portParams)
+case class AHBInternalInputNode(portParams: Seq[AHBMasterPortParameters]) extends InternalInputNode(AHBImp)(portParams)
diff --git a/src/main/scala/uncore/apb/Nodes.scala b/src/main/scala/uncore/apb/Nodes.scala
index 0663875b..f344a0d7 100644
--- a/src/main/scala/uncore/apb/Nodes.scala
+++ b/src/main/scala/uncore/apb/Nodes.scala
@@ -52,8 +52,8 @@ case class APBOutputNode() extends OutputNode(APBImp)
 case class APBInputNode() extends InputNode(APBImp)
 
 // Nodes used for external ports
-case class APBBlindOutputNode(portParams: APBSlavePortParameters) extends BlindOutputNode(APBImp)(portParams)
-case class APBBlindInputNode(portParams: APBMasterPortParameters) extends BlindInputNode(APBImp)(portParams)
+case class APBBlindOutputNode(portParams: Seq[APBSlavePortParameters]) extends BlindOutputNode(APBImp)(portParams)
+case class APBBlindInputNode(portParams: Seq[APBMasterPortParameters]) extends BlindInputNode(APBImp)(portParams)
 
-case class APBInternalOutputNode(portParams: APBSlavePortParameters) extends InternalOutputNode(APBImp)(portParams)
-case class APBInternalInputNode(portParams: APBMasterPortParameters) extends InternalInputNode(APBImp)(portParams)
+case class APBInternalOutputNode(portParams: Seq[APBSlavePortParameters]) extends InternalOutputNode(APBImp)(portParams)
+case class APBInternalInputNode(portParams: Seq[APBMasterPortParameters]) extends InternalInputNode(APBImp)(portParams)
diff --git a/src/main/scala/uncore/axi4/Nodes.scala b/src/main/scala/uncore/axi4/Nodes.scala
index 7d22b666..e31bfaa3 100644
--- a/src/main/scala/uncore/axi4/Nodes.scala
+++ b/src/main/scala/uncore/axi4/Nodes.scala
@@ -52,8 +52,8 @@ case class AXI4OutputNode() extends OutputNode(AXI4Imp)
 case class AXI4InputNode() extends InputNode(AXI4Imp)
 
 // Nodes used for external ports
-case class AXI4BlindOutputNode(portParams: AXI4SlavePortParameters) extends BlindOutputNode(AXI4Imp)(portParams)
-case class AXI4BlindInputNode(portParams: AXI4MasterPortParameters) extends BlindInputNode(AXI4Imp)(portParams)
+case class AXI4BlindOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends BlindOutputNode(AXI4Imp)(portParams)
+case class AXI4BlindInputNode(portParams: Seq[AXI4MasterPortParameters]) extends BlindInputNode(AXI4Imp)(portParams)
 
-case class AXI4InternalOutputNode(portParams: AXI4SlavePortParameters) extends InternalOutputNode(AXI4Imp)(portParams)
-case class AXI4InternalInputNode(portParams: AXI4MasterPortParameters) extends InternalInputNode(AXI4Imp)(portParams)
+case class AXI4InternalOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends InternalOutputNode(AXI4Imp)(portParams)
+case class AXI4InternalInputNode(portParams: Seq[AXI4MasterPortParameters]) extends InternalInputNode(AXI4Imp)(portParams)
diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala
index eac638ba..18d0553e 100644
--- a/src/main/scala/uncore/tilelink2/IntNodes.scala
+++ b/src/main/scala/uncore/tilelink2/IntNodes.scala
@@ -95,11 +95,11 @@ case class IntAdapterNode(
 case class IntOutputNode() extends OutputNode(IntImp)
 case class IntInputNode() extends InputNode(IntImp)
 
-case class IntBlindOutputNode() extends BlindOutputNode(IntImp)(IntSinkPortParameters(Seq(IntSinkParameters())))
-case class IntBlindInputNode(num: Int) extends BlindInputNode(IntImp)(IntSourcePortParameters(Seq(IntSourceParameters(num))))
+case class IntBlindOutputNode() extends BlindOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters()))))
+case class IntBlindInputNode(num: Int) extends BlindInputNode(IntImp)(Seq(IntSourcePortParameters(Seq(IntSourceParameters(num)))))
 
-case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(IntSinkPortParameters(Seq(IntSinkParameters())))
-case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(IntSourcePortParameters(Seq(IntSourceParameters(num))))
+case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters()))))
+case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(Seq(IntSourcePortParameters(Seq(IntSourceParameters(num)))))
 
 class IntXbar()(implicit p: Parameters) extends LazyModule
 {
diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala
index da879180..c0e62707 100644
--- a/src/main/scala/uncore/tilelink2/Nodes.scala
+++ b/src/main/scala/uncore/tilelink2/Nodes.scala
@@ -120,11 +120,11 @@ case class TLOutputNode() extends OutputNode(TLImp)
 case class TLInputNode() extends InputNode(TLImp)
 
 // Nodes used for external ports
-case class TLBlindOutputNode(portParams: TLManagerPortParameters) extends BlindOutputNode(TLImp)(portParams)
-case class TLBlindInputNode(portParams: TLClientPortParameters) extends BlindInputNode(TLImp)(portParams)
+case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters]) extends BlindOutputNode(TLImp)(portParams)
+case class TLBlindInputNode(portParams: Seq[TLClientPortParameters]) extends BlindInputNode(TLImp)(portParams)
 
-case class TLInternalOutputNode(portParams: TLManagerPortParameters) extends InternalOutputNode(TLImp)(portParams)
-case class TLInternalInputNode(portParams: TLClientPortParameters) extends InternalInputNode(TLImp)(portParams)
+case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters]) extends InternalOutputNode(TLImp)(portParams)
+case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends InternalInputNode(TLImp)(portParams)
 
 /** Synthesizeable unit tests */
 import unittest._