riscv/rocket-chip
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diplomacy: support multiple ports behind a BlindNode

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This commit is contained in:
Wesley W. Terpstra
2017-01-19 14:25:34 -08:00
parent 258abc5629
commit e7b35b4bb6
8 changed files with 43 additions and 39 deletions
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20
src/main/scala/rocketchip/Periphery.scala
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@ -91,7 +91,7 @@ trait PeripheryMasterAXI4Mem {
val c_size = config.size/channels
val c_base = config.base + c_size*i
AXI4BlindOutputNode(AXI4SlavePortParameters(
AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(c_base, c_size-1)),
regionType = RegionType.UNCACHED, // cacheable
@ -99,7 +99,7 @@ trait PeripheryMasterAXI4Mem {
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256),
interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = config.beatBytes))
beatBytes = config.beatBytes)))
}
val mem = mem_axi4.map { node =>
@ -130,14 +130,14 @@ trait PeripheryMasterAXI4MMIO {
this: TopNetwork =>
private val config = p(ExtBus)
val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(BigInt(config.base), config.size-1)),
executable = true, // Can we run programs on this memory?
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256),
interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = config.beatBytes))
beatBytes = config.beatBytes)))
mmio_axi4 :=
AXI4Buffer()(
@ -167,9 +167,9 @@ trait PeripheryMasterAXI4MMIOModule {
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
trait PeripherySlaveAXI4 extends L2Crossbar {
private val config = p(ExtIn)
val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << config.idBits)))))
id = IdRange(0, 1 << config.idBits))))))
l2.node :=
TLSourceShrinker(1 << config.sourceBits)(
@ -197,14 +197,14 @@ trait PeripheryMasterTLMMIO {
this: TopNetwork =>
private val config = p(ExtBus)
val mmio_tl = TLBlindOutputNode(TLManagerPortParameters(
val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
managers = Seq(TLManagerParameters(
address = List(AddressSet(BigInt(config.base), config.size-1)),
executable = true,
supportsGet = TransferSizes(1, cacheBlockBytes),
supportsPutFull = TransferSizes(1, cacheBlockBytes),
supportsPutPartial = TransferSizes(1, cacheBlockBytes))),
beatBytes = config.beatBytes))
beatBytes = config.beatBytes)))
mmio_tl :=
TLBuffer()(
@ -233,9 +233,9 @@ trait PeripheryMasterTLMMIOModule {
// NOTE: this port is NOT allowed to issue Acquires
trait PeripherySlaveTL extends L2Crossbar {
private val config = p(ExtIn)
val l2_tl = TLBlindInputNode(TLClientPortParameters(
val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters(
clients = Seq(TLClientParameters(
sourceId = IdRange(0, 1 << config.idBits)))))
sourceId = IdRange(0, 1 << config.idBits))))))
l2.node :=
TLSourceShrinker(1 << config.sourceBits)(

2
src/main/scala/rocketchip/TestHarness.scala
View File

@ -46,7 +46,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
val config = p(ExtMem)
val node = AXI4BlindInputNode(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits)))))
val node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits))))))
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))